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31. 发明申请

US20080249973A1 SYSTEM FOR MANAGING MULTI-FIELD CLASSIFICATION RULES RELATING TO INGRESS CONTEXTS AND EGRESS CONTEXTS 失效
标题翻译：用于管理与生态系统和排气系统有关的多领域分类规则的系统
公开(公告)号：US20080249973A1
公开(公告)日：2008-10-09
申请号：US12143641
申请日：2008-06-20
申请人： Everett A. Corl , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
发明人： Everett A. Corl , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
IPC分类号： G06N5/02
CPC分类号： G06N99/005
摘要： The present invention relates to a system for managing a plurality of multi-field classification rules. The system provides a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The system also includes a network processor for classifying packets of information, wherein the network processor is programmed to utilize the first table and the second table to identify any rules relating to the ingress context and any one rules relating to the egress context that match a search key.
摘要翻译：本发明涉及一种用于管理多个多场分类规则的系统。该系统提供第一表，其包括对应于与入口上下文相关的多个规则的多个条目，以及第二表，其包括对应于与出口上下文相关的多个规则的多个条目。该系统还包括用于对信息包进行分类的网络处理器，其中网络处理器被编程为利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索匹配的出口上下文相关的任何规则键。

32. 发明申请

US20080240110A1 MEMORY SYSTEM WITH APPARATUS AND METHOD TO ENABLE BALANCED BANDWIDTH UTILIZATION 失效
标题翻译：具有装置的存储系统和使用平衡带宽利用的方法
公开(公告)号：US20080240110A1
公开(公告)日：2008-10-02
申请号：US11776162
申请日：2007-07-11
申请人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
发明人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
IPC分类号： H04L12/56
CPC分类号： H04L49/9042 , H04L49/90 , H04L2012/5681
摘要： A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.
摘要翻译：内存子系统包括数据存储0和数据存储1。每个数据存储区分为N个缓冲区，N> 1。存储器的增量由缓冲器对形成，缓冲器对的每个缓冲器在不同的数据存储器中。两个缓冲器对格式用于形成存储器增量。第一种格式从Data Store 0中选择第一个缓冲区，从Data Store 1中选择第二个缓冲区，而第二种格式从Data Store 1中选择第一个缓冲区，从Data Store 0中选择第二个缓冲区。控制器基于诸如交换单元之类的传送机制中的数据的配置来选择用于存储数据的缓冲器对。

33. 发明授权

US07412431B2 Method for managing multi-field classification rules relating to ingress 失效
标题翻译：管理与入口有关的多领域分类规则的方法
公开(公告)号：US07412431B2
公开(公告)日：2008-08-12
申请号：US10832958
申请日：2004-04-27
申请人： Everett A. Corl, Jr. , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
发明人： Everett A. Corl, Jr. , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G06N99/005
摘要： The present invention relates to a method for managing a plurality of multi-field classification rules. The method includes providing a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and providing a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The method also includes utilizing the first table and the second table to identify any rules relating to the ingress context and any rules relating to the egress context that match a search key.
摘要翻译：本发明涉及一种用于管理多个多场分类规则的方法。该方法包括提供第一表格，该第一表格包括对应于与入口上下文有关的多个规则的多个条目，并提供第二表格，该第二表格包括对应于与出口上下文有关的多个规则的多个条目。该方法还包括利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索关键字匹配的出口上下文相关的任何规则。

34. 发明申请

US20080162525A1 SYSTEM FOR DEFINING DATA MAPPINGS BETWEEN DATA STRUCTURES 失效
标题翻译：用于定义数据结构之间数据映射的系统
公开(公告)号：US20080162525A1
公开(公告)日：2008-07-03
申请号：US12048667
申请日：2008-03-14
申请人： Everett A. CORL , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
发明人： Everett A. CORL , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
IPC分类号： G06F17/30
CPC分类号： H03M7/30 , Y10S707/99942
摘要： Method for compressing search tree structures used in rule classification is provided. The method includes classifying packets based on filter rules, compressing a tree structure comprising multiple levels of single bit test nodes and leaf nodes, storing the compressed tree structure in a first memory structure of a storage such that the multiple levels of single bit test nodes and leaf nodes can be accessed from the first memory structure through a single memory access of the storage, collecting single bit test nodes of the tree structure that are in a lowest level of the tree structure, storing only the collected single bit test nodes within a second memory structure of the storage that is contiguous to the first memory structure, collecting leaf nodes of the tree structure, and storing only the collected leaf nodes within a third memory structure of the storage that is contiguous to second memory structure.
摘要翻译：提供了规则分类中使用的搜索树结构的压缩方法。该方法包括基于过滤器规则对分组进行分类，压缩包括多个单位测试节点和叶节点的树结构，将压缩的树结构存储在存储器的第一存储器结构中，使得多个单位测试节点和可以通过存储器的单个存储器访问从第一存储器结构访问叶节点，收集处于树结构的最低级别的树结构的单位测试节点，仅在第二存储器结构中存储所收集的单个位测试节点与第一存储器结构相邻的存储器的存储器结构，收集树结构的叶节点，以及仅存储所收集的叶节点在与第二存储器结构相邻的存储器的第三存储器结构内。

35. 发明授权

US07277982B2 DRAM access command queuing structure 有权
标题翻译： DRAM访问命令排队结构
公开(公告)号：US07277982B2
公开(公告)日：2007-10-02
申请号：US10899937
申请日：2004-07-27
申请人： Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译：访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。仲裁器首先将DRAM访问划分为写访问和读访问。访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。基于写入队列状态，写入接收数据包在存储体之间旋转。每个存储体的写入队列的状态也可以用于系统流控制。仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

36. 发明授权

US07149749B2 Method of inserting and deleting leaves in tree table structures 失效
标题翻译：在树表结构中插入和删除叶子的方法
公开(公告)号：US07149749B2
公开(公告)日：2006-12-12
申请号：US10453245
申请日：2003-06-03
申请人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall , Sonia K. Rovner
发明人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall , Sonia K. Rovner
IPC分类号： G06F17/30
CPC分类号： G06F17/30625 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943
摘要： A technique is provided to either insert or delete a leaf in a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as either a leaf to be inserted or deleted. Using the pattern, the tree is walked once to identify the location of the leaf to be deleted or the location where the leaf is to be inserted. If it is a delete operation, the leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. If it is an insert operation, the tree is walked a second time to insert the leaf and reform or create any PSCB in the chain that needs to be reformed or created. The technique also is applicable to inserting or deleting a prefix of a prefix.
摘要翻译：提供了一种技术来插入或删除具有直接表的Patricia树中的叶子，以及多个PSCB，其解码树中的叶子的图案的部分，而不关闭树的功能。具有图案的叶被识别为要插入或删除的叶。使用图案，树一次走一次，以确定要删除的叶的位置或叶被插入的位置。如果是删除操作，则要删除的叶被识别和删除，并且必要时修改任何相关的PSCB。如果是插入操作，则树第二次移动以插入叶，并在需要重新创建或创建的链中重新构建或创建任何PSCB。该技术也适用于插入或删除前缀的前缀。

37. 发明授权

US06963868B2 Multi-bit Patricia trees 失效
标题翻译：多比特Patricia树
公开(公告)号：US06963868B2
公开(公告)日：2005-11-08
申请号：US10448528
申请日：2003-05-30
申请人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall
发明人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： H04L45/00 , H04L45/56 , H04L45/7457 , Y10S707/99933
摘要： A tree structure and method to organize routing information for processing messages within a network, each message being associated with a search key of “n” bits. The processing determines where to send the message next. The structure has a direct table (DT) of 2x entries for decoding the first “x” bits of the search key, and one or more pattern search control blocks (PSCB's), each having 2m entries for decoding subsequent groups of “m” bits. Each PSCB entry and DT entry includes a pointer to data associated with a specific route, if at this point a specific routing table entry is a potential match to the search key or a pointer to a subsequent PSCB if the end of a search trail is not identified. Each PSCB entry DT entry also indicates that the search has been resolved to the end of the search trail.
摘要翻译：一种用于组织用于处理网络内的消息的路由信息的树结构和方法，每个消息与“n”比特的搜索关键字相关联。该处理确定接下来发送消息的位置。该结构具有用于对搜索关键字的第一个“x”比特进行解码的2个“<”条目的直接表（DT），以及一个或多个模式搜索控制块（PSCB），每个具有2个

38. 发明授权

US5602848A Multi-mode TDM interface circuit 失效
标题翻译：多模TDM接口电路
公开(公告)号：US5602848A
公开(公告)日：1997-02-11
申请号：US460951
申请日：1995-06-05
申请人： Lawrence P. Andrews , Gordon T. Davis , Lee H. House , Baiju D. Mandalia , Laurence V. Marks , William R. Robinson, Jr. , John C. Sinibaldi
发明人： Lawrence P. Andrews , Gordon T. Davis , Lee H. House , Baiju D. Mandalia , Laurence V. Marks , William R. Robinson, Jr. , John C. Sinibaldi
IPC分类号： H04Q11/04 , H04J3/12
CPC分类号： H04Q11/04 , H04Q2213/1305 , H04Q2213/13097 , H04Q2213/13103 , H04Q2213/13213 , H04Q2213/13214 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/1336
摘要： A multi-mode time division multiplexing (TDM) interface circuit for interfacing between a serial data port and a data buffer is provided. The TDM interface circuit contains a transmitter and a receiver section. The circuit is programmable to operate in a variety of modes and is capable of supporting various multi-channel TDM interfaces as well as single channel analog interfaces. The circuit is programmable by writing a control word to a control register. In operation the circuit receives a frame synchronization signal, a gated bit clock signal, and a bit clock signal from the circuit with which it is interfacing on the serial data port. A base address input to a base address register provides up to 9 of the most significant bits of a data buffer address. A 12-bit counter is used to generate the remaining (least significant) bits of the data buffer address according to the control word in the control register.
摘要翻译：提供了用于在串行数据端口和数据缓冲器之间进行接口的多模式时分复用（TDM）接口电路。 TDM接口电路包含发射机和接收机部分。该电路可编程为以各种模式工作，并且能够支持各种多通道TDM接口以及单通道模拟接口。该电路通过将控制字写入控制寄存器来编程。在操作中，电路从串行数据端口接口的电路接收帧同步信号，门控位时钟信号和位时钟信号。输入到基地址寄存器的基地址最多可以提供数据缓冲区地址的最高有效位的9位。根据控制寄存器中的控制字，使用12位计数器产生数据缓冲器地址的剩余（最低有效位）。

39. 发明授权

US4871974A Coherent phase shift keyed demodulator 失效
标题翻译：相干相移键控解调器
公开(公告)号：US4871974A
公开(公告)日：1989-10-03
申请号：US289064
申请日：1988-12-23
申请人： Gordon T. Davis , Baiju D. Mandalia
发明人： Gordon T. Davis , Baiju D. Mandalia
IPC分类号： H04L27/22 , H04L27/227
CPC分类号： H04L27/2275
摘要： A demodulator mechanism which uses estimates of the in-phase and quadrature-phase components of differential phase modulated carrier signals for performing a coherent demodulation of these signals is described. The instantaneous estimates, obtained from an estimator circuit, are fed into a differential carrier recovery circuit, which provides for a feedback of ideal sine and cosine components, and combined with the instantaneous estimates for incrementally decreasing a phase error signal generated in a computational circuit. By thus incrementally decreasing the phase error signal, an ideal phase angle is eventually obtained, thereby providing for coherent demodulated output components of the input carrier signals.

40. 发明授权

US08386712B2 Structure for supporting simultaneous storage of trace and standard cache lines 失效
标题翻译：用于支持跟踪和标准缓存行同时存储的结构
公开(公告)号：US08386712B2
公开(公告)日：2013-02-26
申请号：US12116676
申请日：2008-05-07
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/0897 , G06F2212/6082
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
摘要翻译：体现在用于设计，制造和/或测试用于单个统一级别的一个指令高速缓存的机器可读存储介质中的设计结构，其中一些行可以包含跟踪和相同同余类中的其他行的设计可以包含一致的指令块提供常规的高速缓存线。描述了一种用于索引到缓存中并选择所需行的机制。对缓存中包含哪些行进行控制。当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。

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