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31. 发明授权

US08296345B2 Microprocessor with selectively available random number generator based on self-test result 有权
标题翻译：基于自检结果的具有选择性可用随机数发生器的微处理器
公开(公告)号：US08296345B2
公开(公告)日：2012-10-23
申请号：US11611865
申请日：2006-12-16
申请人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
发明人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
IPC分类号： G06F1/02
CPC分类号： G06F7/58 , G06F9/30003 , G06F9/3004 , G06F9/30087 , G06F11/27
摘要： A microprocessor including a random number generator within its instruction set architecture and made selectively available to program instructions of the instruction set architecture depending upon results of a self-test of the random number generator performed is disclosed. The microprocessor also includes a self-test unit that performs the self-test in response to a reset. The microprocessor also includes an instruction translator that translates instructions of the instruction set architecture, including instructions related exclusively to operation of the random number generator. The microprocessor generates a fault defined by the instruction set architecture in response to execution of one of the plurality of instructions related exclusively to operation of the random number generator if the self-test unit previously determined the random number generator is not operating properly.
摘要翻译：公开了一种微处理器，其包括在其指令集架构内的随机数发生器，并且被选择性地可用于根据执行的随机数发生器的自检的结果对指令集架构的指令进行编程。微处理器还包括自检单元，其响应于复位来执行自检。微处理器还包括一个指令转换器，其转换指令集架构的指令，包括专门涉及随机数发生器操作的指令。如果自检单元先前确定的随机数发生器不能正常工作，则微处理器响应于专用于随机数发生器的操作的多个指令之一的执行而产生由指令集结构定义的故障。

32. 发明申请

US20110296204A1 MICROPROCESSOR THAT FACILITATES TASK SWITCHING BETWEEN ENCRYPTED AND UNENCRYPTED PROGRAMS 有权
标题翻译：加密程序和未经许可的程序之间的任何需要切换的微处理器
公开(公告)号：US20110296204A1
公开(公告)日：2011-12-01
申请号：US13091698
申请日：2011-04-21
申请人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F21/00
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A microprocessor includes an architected register having a bit (may be x86 EFLAGS register reserved bit) set by the microprocessor. A fetch unit fetches encrypted instructions from an instruction cache and decrypts them (via XOR) prior to executing them, in response to the microprocessor setting the bit. The microprocessor saves the bit value to a stack in memory and then clears the bit in response to receiving an interrupt. The fetch unit fetches unencrypted instructions from the instruction cache and executes them without decrypting them after the microprocessor clears the bit. The microprocessor restores the saved value from the stack in memory to the bit in the architected register (and in one embodiment, also restores decryption key values) in response to executing a return from interrupt instruction. The fetch unit resumes fetching and decrypting the encrypted instructions in response to determining that the restored value of the bit is set.
摘要翻译：微处理器包括由微处理器设置的位（可以是x86 EFLAGS寄存器保留位）的架构化寄存器。读取单元从指令高速缓存中获取加密指令，并在执行它们之前对其进行解密（通过XOR），以响应微处理器设置该位。微处理器将位值保存到存储器中的堆栈，然后响应于接收到中断而清除该位。提取单元从指令高速缓存中提取未加密的指令，并在微处理器清零位之后执行它们而不对其进行解密。响应于执行中断指令的返回，微处理器将存储器中的保存值从存储器中的位恢复到构造寄存器中的位（并且在一个实施例中，还恢复解密密钥值）。响应于确定该位的恢复值被设置，获取单元恢复取出和解密加密指令。

33. 发明申请

US20110296202A1 SWITCH KEY INSTRUCTION IN A MICROPROCESSOR THAT FETCHES AND DECRYPTS ENCRYPTED INSTRUCTIONS 有权
标题翻译：在微处理器中切换主要指令，并加密指令
公开(公告)号：US20110296202A1
公开(公告)日：2011-12-01
申请号：US13091547
申请日：2011-04-21
申请人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F21/22
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A fetch unit fetches a sequence of blocks of encrypted instructions of an encrypted program from an instruction cache at a corresponding sequence of fetch address values. While fetching each block of the sequence, the fetch unit generates a decryption key as a function of key values and the corresponding fetch address value, and decrypts the encrypted instructions using the generated decryption key by XORing them together. A switch key instruction instructs the microprocessor to update the key values in the fetch unit while the fetch unit is fetching the sequence of blocks. The fetch unit inherently provides an effective decryption key length that depends upon the function and amount of key values used. Including one or more switch key instructions within the encrypted program increases the effective decryption key length up to the encrypted program length.
摘要翻译：取出单元以相应的获取地址值序列从指令高速缓存中提取加密程序的加密指令的一系列块。在提取序列的每个块时，提取单元根据密钥值和相应的获取地址值产生解密密钥，并且通过将它们一起进行异或来解密加密的指令。切换键指令指示微处理器在获取单元获取块序列时更新提取单元中的键值。提取单元固有地提供了一个有效的解密密钥长度，这取决于所使用的密钥值的功能和数量。在加密程序中包括一个或多个切换密钥指令将有效的解密密钥长度增加到加密的程序长度。

34. 发明申请

US20110142228A1 APPARATUS AND METHOD FOR EMPLOYING CONFIGURABLE HASH ALGORITHMS 有权
标题翻译：使用可配置的哈希算法的装置和方法
公开(公告)号：US20110142228A1
公开(公告)日：2011-06-16
申请号：US12977803
申请日：2010-12-23
申请人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
发明人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
IPC分类号： H04L9/28
CPC分类号： H04L9/3239 , G06F9/30007 , G06F9/30065 , G06F9/30185 , G06F9/3895 , G06F21/64 , G06F21/72 , H04L9/0643 , H04L2209/125 , H04L2209/60
摘要： A method for performing hash operations including: receiving a hash instruction that is part of an application program, where the hash instruction prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit disposed within execution logic, executing the one of the hash operations. The executing includes first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.
摘要翻译：一种用于执行散列操作的方法，包括：接收作为应用程序的一部分的散列指令，其中所述散列指令规定所述散列操作之一和多个散列算法之一; 将所述散列指令转换成第一多个微指令和第二多个微指令; 并且经由布置在执行逻辑内的哈希单元，执行所述散列操作之一。所述执行包括首先执行所述散列单元内的所述第一多个微指令以产生输出数据; 第二执行x86整数单元内的第二多个微指令，与第一次执行一起执行以测试标志寄存器中的位，更新文本指针寄存器，以及在执行散列操作期间处理中断; 以及在允许待决中断进行之前将相应的中间散列值存储到存储器。

35. 发明授权

US07900055B2 Microprocessor apparatus and method for employing configurable block cipher cryptographic algorithms 有权
标题翻译：用于采用可配置块密码加密算法的微处理器装置和方法
公开(公告)号：US07900055B2
公开(公告)日：2011-03-01
申请号：US10800938
申请日：2004-03-15
申请人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
发明人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
IPC分类号： G06F12/14
CPC分类号： G06F9/30181 , G06F9/30003 , G06F9/30007 , G06F9/30174 , G06F9/3877 , G06F21/72 , H04L9/0637 , H04L2209/125
摘要： An apparatus for performing cryptographic operations. The apparatus includes an x86-compatible microprocessor that has fetch logic, algorithm logic, and execution logic. The fetch logic is configured to receive a single, atomic cryptographic instruction as one of the instructions in an application program executing on the x86-compatible microprocessor. The single, atomic cryptographic instruction prescribes an encryption operation and one of a plurality of cryptographic algorithms. The algorithm logic is operatively coupled to the single, atomic cryptographic instruction. The algorithm logic directs the x86-compatible microprocessor to execute the encryption operation according to the one of a plurality of cryptographic algorithms. The execution logic is operatively coupled to the algorithm logic. The execution logic executes the encryption operation. The execution logic includes a cryptography unit for executing a plurality of cryptographic rounds required to complete the encryption operation.
摘要翻译：一种用于执行加密操作的装置。该装置包括具有提取逻辑，算法逻辑和执行逻辑的x86兼容微处理器。提取逻辑被配置为接收作为在x86兼容微处理器上执行的应用程序中的指令之一的单个原子加密指令。单个原子加密指令规定了加密操作和多个密码算法之一。算法逻辑可操作地耦合到单个原子加密指令。算法逻辑指示x86兼容微处理器根据多个密码算法中的一种进行加密操作。执行逻辑可操作地耦合到算法逻辑。执行逻辑执行加密操作。执行逻辑包括用于执行完成加密操作所需的多个加密轮的加密单元。

36. 发明授权

US07532722B2 Apparatus and method for performing transparent block cipher cryptographic functions 有权
标题翻译：用于执行透明块密码加密功能的装置和方法
公开(公告)号：US07532722B2
公开(公告)日：2009-05-12
申请号：US10727973
申请日：2003-12-04
申请人： Thomas A. Crispin , G. Glenn Henry , Arturo Martin-de-Nicolas , Terry Parks
发明人： Thomas A. Crispin , G. Glenn Henry , Arturo Martin-de-Nicolas , Terry Parks
IPC分类号： H04L9/00
CPC分类号： G06F9/3001 , G06F9/30007 , G06F9/30043 , G06F9/3017 , G06F9/30178 , G06F9/325 , G06F9/3885 , G06F21/72 , H04L9/0631 , H04L9/0637 , H04L2209/125 , H04L2209/24
摘要： The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction and execution logic. The cryptographic instruction is received by a computing device as part of an instruction flow executing on the computing device, wherein the cryptographic instruction prescribes one of the cryptographic operations. The execution logic is operatively coupled to the cryptographic instruction and executes the one of the cryptographic operations. The one of the cryptographic operations includes indicating whether the one of the cryptographic operations has been interrupted by an interrupting event.
摘要翻译：本发明提供一种用于对处理器内的多个输入数据块执行密码操作的装置和方法。在一个实施例中，提供了一种用于执行密码操作的装置。该装置包括密码指令和执行逻辑。密码指令由计算设备接收，作为在计算设备上执行的指令流的一部分，其中密码指令规定了一个密码操作。执行逻辑可操作地耦合到密码指令，并执行加密操作之一。加密操作之一包括指示密码操作中的一个是否已被中断事件中断。

37. 发明授权

US09274795B2 Conditional non-branch instruction prediction 有权
标题翻译：条件非分支指令预测
公开(公告)号：US09274795B2
公开(公告)日：2016-03-01
申请号：US13413258
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30076 , G06F9/30112 , G06F9/3017 , G06F9/30189 , G06F9/30196
摘要： A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction. In the case of a misprediction, the translator re-translates the conditional non-branch instruction into the second set of microinstructions.
摘要翻译：微处理器处理指定条件的条件非分支指令，并指示微处理器在条件满足的情况下执行操作，否则不执行操作。预测器提供关于条件非分支指令的预测。当预测预测条件不满足时，指令翻译器将条件非分支指令转换为无操作微指令，并且当预测预测条件将被满足时，指令转换为一组或多个微指令以无条件地执行操作。执行流水线执行无操作微指令或微指令集。当预测不进行预测时，预测器转换成第二组一个或多个微指令以有条件地执行操作。在错误预测的情况下，翻译者将条件非分支指令重新翻译成第二组微指令。

38. 发明授权

US09146742B2 Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA 有权
标题翻译：异构ISA微处理器在复位到不同的ISA时保留非ISA特定的配置状态
公开(公告)号：US09146742B2
公开(公告)日：2015-09-29
申请号：US13412914
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/48 , G06F9/50 , G06F9/54 , G06F9/30 , G06F9/38 , G06F9/46
CPC分类号： G06F9/30174 , G06F9/3017 , G06F9/30181 , G06F9/30189 , G06F9/3844 , G06F9/461
摘要： A microprocessor capable of operating as both an x86 ISA and an ARM ISA microprocessor includes first, second, and third storage that stores x86 ISA-specific, ARM ISA-specific, and non-ISA-specific state, respectively. When reset, the microprocessor initializes the first storage to default values specified by the x86 ISA, initializes the second storage to default values specified by the ARM ISA, initializes the third storage to predetermined values, and begins fetching instructions of a first ISA. The first ISA is the x86 ISA or the ARM ISA and a second ISA is the other ISA. The microprocessor updates the third storage in response to the first ISA instructions. In response to a subsequent one of the first ISA instructions that instructs the microprocessor to reset to the second ISA, the microprocessor refrains from modifying the non-ISA-specific state stored in the third storage and begins fetching instructions of the second ISA.
摘要翻译：能够同时运行x86 ISA和ARM ISA微处理器的微处理器分别包含第一，第二和第三存储，它们分别存储特定于x86 ISA特定的ISA特定状态和非ISA特定状态。当复位时，微处理器将第一个存储器初始化为由x86 ISA指定的默认值，将第二个存储初始化为由ARM ISA指定的默认值，将第三个存储初始化为预定值，并开始获取第一个ISA的指令。第一个ISA是x86 ISA或ARM ISA，另一个ISA是另一个ISA。微处理器响应于第一ISA指令更新第三存储器。响应于指示微处理器重置到第二ISA的第一ISA指令中的随后的一个，微处理器不修改存储在第三存储器中的非ISA特定状态，并开始获取第二ISA的指令。

39. 发明授权

US09128701B2 Generating constant for microinstructions from modified immediate field during instruction translation 有权
标题翻译：在指导翻译过程中，从修改的立即场产生微指令的常数
公开(公告)号：US09128701B2
公开(公告)日：2015-09-08
申请号：US13416879
申请日：2012-03-09
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30072 , G06F9/30094 , G06F9/30112 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3806
摘要： An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a constant value as one of its source operands. The constant value is the first value rotated/shifted by a number of bits based on the second value. An instruction translator translates the instruction into one or more microinstructions. An execution pipeline executes the microinstructions generated by the instruction translator. The instruction translator, rather than the execution pipeline, generates the constant value for the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline. Alternatively, if the immediate field value is not within a predetermined subset of values known by the instruction translator, the instruction translator generates, rather than the constant, a second microinstruction for execution by the execution pipeline to generate the constant.
摘要翻译： ISA定义的指令包括具有指定第一和第二值的第一和第二部分的立即字段，其指示微处理器使用常数值作为其源操作数之一执行操作。常数值是基于第二值旋转/移位多个位的第一值。指令翻译器将指令转换为一个或多个微指令。执行流水线执行指令转换器生成的微指令。指令转换器而不是执行流水线，将执行流水线的常量值作为执行流水线执行的至少一个微指令的源操作数。或者，如果立即字段值不在指令转换器已知的值的预定子集内，则指令转换器生成第二微指令而不是常数，用于由执行流水线执行以产生常数。

40. 发明授权

US09032189B2 Efficient conditional ALU instruction in read-port limited register file microprocessor 有权
标题翻译：读端口限制寄存器文件微处理器中有效的条件ALU指令
公开(公告)号：US09032189B2
公开(公告)日：2015-05-12
申请号：US13333520
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30072 , G06F9/30094 , G06F9/30141 , G06F9/30174
摘要： A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.
摘要翻译：一种微处理器，其执行结构指令，指示其在第一和第二源操作数上执行操作以产生结果，并且仅当其结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。硬件指令转换器将指令转换为第一和第二微指令。要执行第一个微指令，执行流水线对源操作数执行操作以生成结果。要执行第二个微指令，如果架构条件标志满足条件，则将目标寄存器写入由第一微指令生成的结果，如果结构条件标志不满足条件标志，则将目标寄存器写入目标寄存器的当前值条件。

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