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31. 发明授权

US06884683B2 Trench DMOS transistor having a zener diode for protection from electro-static discharge 有权
标题翻译：沟槽DMOS晶体管具有用于防止静电放电的齐纳二极管
公开(公告)号：US06884683B2
公开(公告)日：2005-04-26
申请号：US10714807
申请日：2003-11-18
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L27/04 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L29/49 , H01L29/78 , H01L29/866
CPC分类号： H01L29/7813 , H01L29/4916 , H01L29/7808 , H01L2924/0002 , H01L2924/00
摘要： A trench DMOS transistor having overvoltage protection includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer. A plurality of cathode regions of the first conductivity type are formed in the undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions.
摘要翻译：具有过电压保护的沟槽DMOS晶体管包括形成在衬底上的第一导电类型的衬底和第二导电类型的体区。至少一个沟槽延伸穿过身体区域和衬底。绝缘层在沟槽上划线并覆盖在身体区域上。导电电极沉积在沟槽中，使其覆盖绝缘层。第一导电类型的源区形成在与沟槽相邻的体区中。未掺杂的多晶硅层覆盖绝缘层的一部分。在未掺杂多晶硅层中形成第一导电类型的多个阴极区。至少一个阳极区域与多个阴极区域中的相邻阳极区域接触。

32. 发明授权

US06627951B2 High speed trench DMOS 有权
标题翻译：高速沟DMOS
公开(公告)号：US06627951B2
公开(公告)日：2003-09-30
申请号：US09882117
申请日：2001-06-15
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/4232 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4916 , H01L29/4925 , H01L29/4933
摘要： A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.
摘要翻译：提供了制造沟槽DMOS的方法，其利用多硅化物和难熔技术来制造出具有低栅极电阻，低栅极电容，降低的分布式RC栅极传播延迟以及用于高频应用的改进的开关速度的沟槽DMOS。

33. 发明授权

US06472678B1 Trench MOSFET with double-diffused body profile 有权
标题翻译：具有双扩散体轮廓的沟槽MOSFET
公开(公告)号：US06472678B1
公开(公告)日：2002-10-29
申请号：US09595486
申请日：2000-06-16
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/7811
摘要： A trench MOSFET device and process for making the same are described. The trench MOSFET has a substrate of a first conductivity type, an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate, a plurality of trenches within the epitaxial layer, a first insulating layer, such as an oxide layer, lining the trenches, a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer, and one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions. Each trench body region and each termination body region has a first region of a second conductivity type, the second conductivity type being opposite the first conductivity type, and a second region of the second conductivity type adjacent the first region, the second region having a greater majority carrier concentration than the first region, and the second region being disposed above the first region and adjacent and extending to an outer wall of each of the plurality of trenches. A plurality of source regions of the first conductivity type are positioned adjacent the trenches within upper portions the trench body regions.
摘要翻译：描述了沟槽MOSFET器件及其制造方法。沟槽MOSFET具有第一导电类型的衬底，在衬底上的第一导电类型的外延层，外延层具有比衬底更低的多数载流子浓度，外延层内的多个沟槽，第一绝缘层，诸如沟槽衬里的氧化物层，在与第一绝缘层相邻的沟槽内的导电区域，例如多晶硅区域，以及一个或多个沟槽体区域和设置在上部的一个或多个端接体区域外延层的一部分，终端体区域延伸到外延层中比沟槽体区域更深的深度。每个沟槽体区域和每个终端体区域具有第二导电类型的第一区域，第二导电类型与第一导电类型相反，第二导电类型的第二区域与第一区域相邻，第二区域具有更大的多数载流子浓度比第一区域多，并且第二区域设置在第一区域上方并且相邻并延伸到多个沟槽中的每一个的外壁。第一导电类型的多个源极区域位于沟槽体区域的上部内的沟槽附近。

34. 发明授权

US06979621B2 Trench MOSFET having low gate charge 有权
标题翻译：沟槽MOSFET栅极电荷低
公开(公告)号：US06979621B2
公开(公告)日：2005-12-27
申请号：US10751687
申请日：2004-01-05
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/28185 , H01L21/28194 , H01L29/42368 , H01L29/4925 , H01L29/4933 , H01L29/511 , H01L29/513
摘要： A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.
摘要翻译：一种沟槽MOSFET器件，包括：（a）第一导电类型（优选N型导电性）的硅衬底; （b）在衬底上的第一导电类型的硅外延层，所述外延层具有比衬底更低的载流子浓度; （c）在所述外延层的上部内具有第二导电类型（优选P型导电性）的体区; （d）具有沟槽侧壁和沟槽底部的沟槽，其从外延层的上表面延伸到外延层并穿过器件的本体区域; （f）衬在所述沟槽上的氧化物区域，其包括覆盖至少所述沟槽底部的下部段和覆盖所述沟槽侧壁的至少上部区域的上段; （g）邻近氧化物区域的沟槽内的导电区域; 和（h）第一导电类型的源极区域，位于主体区域的上部并且与沟槽相邻。在本实施例中，氧化物区域的下段比氧化物区域的上部段更厚。

35. 发明授权

US06674124B2 Trench MOSFET having low gate charge 有权
标题翻译：沟槽MOSFET栅极电荷低
公开(公告)号：US06674124B2
公开(公告)日：2004-01-06
申请号：US10002529
申请日：2001-11-15
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L21/28185 , H01L21/28194 , H01L29/42368 , H01L29/4925 , H01L29/4933 , H01L29/511 , H01L29/513
摘要： A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.
摘要翻译：一种沟槽MOSFET器件，包括：（a）第一导电类型（优选N型导电性）的硅衬底; （b）在衬底上的第一导电类型的硅外延层，所述外延层具有比衬底更低的载流子浓度; （c）在所述外延层的上部内具有第二导电类型（优选P型导电性）的体区; （d）具有沟槽侧壁和沟槽底部的沟槽，其从外延层的上表面延伸到外延层并穿过器件的本体区域; （f）衬在所述沟槽上的氧化物区域，其包括覆盖至少所述沟槽底部的下部段和覆盖所述沟槽侧壁的至少上部区域的上段; （g）邻近氧化物区域的沟槽内的导电区域; 和（h）第一导电类型的源极区域，位于主体区域的上部并且与沟槽相邻。在本实施例中，氧化物区域的下段比氧化物区域的上部段更厚。

36. 发明授权

US06657255B2 Trench DMOS device with improved drain contact 有权
标题翻译：沟槽DMOS器件具有改善的漏极接触
公开(公告)号：US06657255B2
公开(公告)日：2003-12-02
申请号：US10021419
申请日：2001-10-30
申请人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/41741 , H01L29/41766 , H01L29/7809 , H01L29/7811
摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.
摘要翻译：一种沟槽DMOS晶体管器件，其包括：（a）第一导电类型的衬底; （b）在所述衬底上的第一导电类型的外延层，其中所述外延层具有比所述衬底更低的载流子浓度; （c）从外延层的上表面延伸到外延层中的沟槽; （d）衬在所述沟槽的至少一部分上的绝缘层; （e）邻近绝缘层的沟槽内的导电区域; （f）设置在所述外延层的上部并且与所述沟槽相邻的第二导电类型的体区; （g）第一导电类型的源区域，位于本体区域的上部并且与沟槽相邻; 和（h）从外延层的上表面延伸到器件中的一个或多个低电阻率深区域。低电阻率深区用于与衬底电接触，衬底是衬底的共用漏极区。通过以这种方式构造沟槽DMOS晶体管器件，源极，漏极和栅极触点都可以设置在器件的单个表面上。

37. 发明授权

US06518621B1 Trench DMOS transistor having reduced punch-through 有权
公开(公告)号：US06518621B1
公开(公告)日：2003-02-11
申请号：US09395790
申请日：1999-09-14
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4916
摘要： A method of forming a trench DMOS transistor is provides which reduces punch-through. The method begins by providing a substrate of a first conductivity type. A body region, which has a second conductivity type, is formed on the substrate. A masking layer is formed which defines at least one trench. Next, the trench and an insulating layer that lines the trench are formed. A conductive electrode is then formed in the trench, which overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. The step of forming the trench includes the steps of etching the trench and smoothing the sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.

38. 发明授权

US06312993B1 High speed trench DMOS 有权
标题翻译：高速沟DMOS
公开(公告)号：US06312993B1
公开(公告)日：2001-11-06
申请号：US09515749
申请日：2000-02-29
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/4232 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4916 , H01L29/4925 , H01L29/4933
摘要： A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.
摘要翻译：提供了制造沟槽DMOS的方法，其利用多硅化物和难熔技术来制造出具有低栅极电阻，低栅极电容，降低的分布式RC栅极传播延迟以及用于高频应用的改进的开关速度的沟槽DMOS。

39. 发明授权

US6025230A High speed MOSFET power device with enhanced ruggedness fabricated by simplified processes 失效
标题翻译：高速MOSFET功率器件，通过简化的工艺制造出增强的耐用性
公开(公告)号：US6025230A
公开(公告)日：2000-02-15
申请号：US965349
申请日：1997-11-06
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21/336 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/78 , H01L21/76
CPC分类号： H01L29/402 , H01L29/42372 , H01L29/66712 , H01L29/7802 , H01L29/7813 , H01L29/0638
摘要： This invention discloses a MOSFET power device supported on a substrate. The MOSFET power device includes a plurality polysilicon-with-oxide-cap segments disposed over a gate oxide layer including two outermost segments and a plurality of inner segments include a plurality of gate oxide-plug openings. Each of the inner segments functions as agate and the two outer most segments function as a field plate and an equal potential ring separated by a termination oxide-plug gap and the gate oxide-plug openings and the termination oxide-plug gap having an aspect ratio greater or equal to 0.5. The MOSFET power device further includes a plurality of MOSFET transistor cells for each of the gates, wherein each transistor cells further includes a source region, a body region, the transistor cells further having a common drain disposed at a bottom surface of the substrate. Each of the inner segments functions as a gate having a side wall spacer surrounding edges of the inner segments, and the gate oxide-plug openings and the termination oxide-plug gap being filled with an oxide plug. The MOSFET transistor cells are covered by an overlying insulation layer having a plurality of contact openings defined therein. The MOSFET power device further includes a plurality of metal segments covering the overlying insulation layer and being in electric contact with the DMOS device through the contact opening. The MOSFET power device further includes a plurality of deep-and-narrow gaps between the metal segments wherein each gap having an aspect ratio equal to or greater than 0.5.
摘要翻译：本发明公开了一种支撑在基板上的MOSFET功率器件。 MOSFET功率器件包括设置在包括两个最外部段的栅极氧化物层之上的多个多晶硅 - 氧化物 - 盖段，并且多个内部段包括多个栅极氧化物 - 塞子开口。每个内部区段用作玛瑙，并且两个最外面的区段用作场板和由终止氧化物 - 塞子间隙分开的等电位环，并且栅极氧化物 - 塞子开口和终止氧化物 - 塞子间隙具有纵横比大于或等于0.5。 MOSFET功率器件还包括用于每个栅极的多个MOSFET晶体管单元，其中每个晶体管单元还包括源极区域，体区域，晶体管单元还具有布置在衬底底表面处的共同漏极。每个内部区段用作具有围绕内部段的边缘的侧壁间隔件的栅极，并且栅极氧化物 - 塞子开口和终止氧化物 - 塞子间隙填充有氧化物塞。 MOSFET晶体管单元由其上限定有多个接触开口的上覆绝缘层覆盖。 MOSFET功率器件还包括覆盖上覆绝缘层的多个金属段，并通过接触开口与DMOS器件电接触。 MOSFET功率器件还包括在金属段之间的多个深而窄的间隙，其中每个间隙具有等于或大于0.5的纵横比。

40. 发明授权

US06977203B2 Method of forming narrow trenches in semiconductor substrates 有权
标题翻译：在半导体衬底中形成窄沟槽的方法
公开(公告)号：US06977203B2
公开(公告)日：2005-12-20
申请号：US10010162
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
IPC分类号： H01L21/28 , H01L21/3065 , H01L21/308 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/311 , H01L21/3205
CPC分类号： H01L21/3088 , H01L21/3086
摘要： A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconductor substrate; (c) depositing a second CVD-deposited masking material layer over the first masking material layer; (d) etching the second masking material layer until a second aperture that is narrower than the first aperture is created in the second masking material within the first aperture; and (e) etching the semiconductor substrate through the second aperture such that a trench is formed in the semiconductor substrate. In preferred embodiments, the method of the present invention is used in the formation of trench MOSFET devices.
摘要翻译：一种在半导体衬底内形成沟槽的方法。该方法例如包括以下：（a）提供半导体衬底; （b）提供在半导体衬底上具有第一孔的图案化的第一CVD沉积掩模材料层; （c）在所述第一掩蔽材料层上沉积第二CVD沉积的掩模材料层; （d）蚀刻所述第二掩模材料层，直到在所述第一孔径内的所述第二掩模材料中产生比所述第一孔径窄的第二孔径; 以及（e）通过所述第二孔蚀刻所述半导体衬底，使得在所述半导体衬底中形成沟槽。在优选实施例中，本发明的方法用于形成沟槽MOSFET器件。

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