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31. 发明授权

US6107129A Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance 失效
标题翻译：具有多个LDD和/或源极/漏极注入步骤以增强电路性能的集成电路
公开(公告)号：US6107129A
公开(公告)日：2000-08-22
申请号：US38511
申请日：1998-03-11
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L29/72
CPC分类号： H01L29/6659 , H01L29/7833 , H01L29/7835
摘要： An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.
摘要翻译：形成集成电路，由此产生提高集成电路总体速度的MOS晶体管结。晶体管结包括多个注入到结点的轻掺杂漏极（LDD）区域，结点的源极/漏极区域以及LDD和源极/漏极区域两者。多个植入物的第一植入物用于调节植入区域，使得第二和随后的植入物以相对高的浓度精确地放置在基底表面附近。因此，所得到的结是具有相对高的驱动强度，低接触电阻率，低的源到漏寄生电阻和相对低的结电容的结。

32. 发明授权

US6090694A Local interconnect patterning and contact formation 失效
标题翻译：局部互连图案和接触形成
公开(公告)号：US6090694A
公开(公告)日：2000-07-18
申请号：US991742
申请日：1997-12-16
申请人： Fred N. Hause , Charles E. May , Mark I. Gardner
发明人： Fred N. Hause , Charles E. May , Mark I. Gardner
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/76832 , Y10S438/952
摘要： A method for forming a semiconductor device to produce a more distortion free via for interconnecting levels within a device or forming a connection between an external surface and an internal layer within a device includes the step of substituting a material similar to an etch stop adjacent one of the layers for the ARC. In other words, an etch stop is placed over the metal layer formed on a layer within the device. This is followed by a layer of silicon dioxide (SiO.sub.2) and then by a layer of material similar to the etch stop. Photoresist is placed on the layer of material similar to etch stop. The photoresist is exposed to light to form the location of the vias. The layer of material similar to etch stop, and the SiO.sub.2 layer are then removed in separate etching steps to form the via pathway from the resist to the etch stop adjacent the metal of the layer selected to be interconnected by the via. The resist can then be removed. This leaves the material similar to the etch stop located adjacent one surface of the SiO.sub.2 layer, and leaves the etch stop covering the metal in the via opening. One etch step can now be used to remove the etch stop covering the metal in the via opening and to remove the material similar to the etch stop located on the SiO.sub.2.
摘要翻译：用于形成半导体器件以产生用于在器件内互连电平或形成器件中的外表面和内部层之间的连接的无失真通孔的方法包括以下步骤：将与蚀刻停止相邻的材料 ARC的层。换句话说，蚀刻停止放置在形成在器件内的层上的金属层上。之后是二氧化硅层（SiO 2），然后是与蚀刻停止层相似的材料层。光刻胶放置在与蚀刻停止相似的材料层上。光致抗蚀剂暴露于光以形成通孔的位置。类似于蚀刻停止的材料层，然后在单独的蚀刻步骤中去除SiO 2层，以形成从抗蚀剂到蚀刻停止件的通孔路径，该蚀刻停止件邻近选定为由通孔相互连接的层的金属。然后可以除去抗蚀剂。这使得材料类似于位于SiO 2层的一个表面附近的蚀刻停止层，并且使蚀刻停止件覆盖通孔孔中的金属。现在可以使用一个蚀刻步骤去除覆盖通孔开口中的金属的蚀刻停止层，并且去除类似于位于SiO 2上的蚀刻停止层的材料。

33. 发明授权

US6049133A Semiconductor fabrication employing concurrent diffusion barrier and salicide formation 失效
标题翻译：采用同时扩散阻挡层和自对准硅化物形成的半导体制造
公开(公告)号：US6049133A
公开(公告)日：2000-04-11
申请号：US822121
申请日：1997-03-21
申请人： Fred N. Hause , Mark I. Gardner
发明人： Fred N. Hause , Mark I. Gardner
IPC分类号： H01C1/14 , H01C10/32 , H01C13/00 , H01C17/00 , H01L21/285 , H01L21/336 , H01L21/768 , H01L29/78
CPC分类号： H01L29/7833 , H01C10/32 , H01L21/28518 , H01L21/76841 , H01L21/76855 , H01L21/76856 , H01L29/665 , H01L29/6659
摘要： An integrated circuit fabrication process is provided in which a metal salicide and a diffusion barrier are formed concurrently. This process includes doping regions of a silicon substrate which are spaced apart by a polysilicon gate conductor, thereby forming source/drain junctions within the substrate upper surface. Oxide spacers are located on opposite sidewall surfaces of the gate conductor. The resulting semiconductor topography is then placed within a chamber having a pressurized and heated nitrogen ambient. A metal, i.e., titanium is deposited upon the semiconductor topography, and then annealing of the metal occurs. The titanium metal reacts with silicon at interfaces not containing nitrogen atoms, i.e., exclusive of the oxide spacers, to form titanium salicide. Concurrent with this reaction is the formation of titanium nitride upon the titanium metal. Finally, aluminum is deposited upon the titanium nitride to complete metallization. The titanium nitride diffusion barrier prevents aluminum spiking of the doped junctions below.
摘要翻译：提供了同时形成金属硅化物和扩散阻挡层的集成电路制造工艺。该工艺包括由多晶硅栅极导体隔开的硅衬底的掺杂区域，从而在衬底上表面内形成源极/漏极结。氧化物间隔物位于栅极导体的相对侧壁表面上。然后将所得半导体形貌放置在具有加压和加热的氮气环境的室内。在半导体形貌上沉积金属，即钛，然后发生金属的退火。钛金属在不含氮原子的界面（即不包括氧化物间隔物）与硅反应形成硅化硅。与此反应同时在钛金属上形成氮化钛。最后，铝沉积在氮化钛上以完成金属化。氮化钛扩散阻挡层阻止下述掺杂结的铝尖峰。

34. 发明授权

US6046471A Ultra shallow junction depth transistors 失效
标题翻译：超浅结深度晶体管
公开(公告)号：US6046471A
公开(公告)日：2000-04-04
申请号：US744405
申请日：1996-11-07
申请人： Mark I. Gardner , Fred N. Hause , Daniel Kadosh
发明人： Mark I. Gardner , Fred N. Hause , Daniel Kadosh
IPC分类号： H01L21/265 , H01L21/336 , H01L31/119
CPC分类号： H01L29/66575 , H01L21/2652
摘要： A shallow junction MOS transistor comprising a semiconductor substrate having an upper region that includes a first and a second lightly doped region laterally displaced on either side of the channel region. The first and second lightly doped regions extend to a junction depth below the upper surface of the semiconductor substrate. A first and a second lightly doped impurity distribution are located within the first and second source/drain regions of the semiconductor substrate. The shallow junction transistor further includes a gate dielectric formed on an upper surface of the channel region of the semiconductor substrate. A conductive gate that includes a first and a second sidewall is formed on the gate dielectric. A gate insulator is formed in contact with the first and second sidewalls of the conductive gate. First and second source/drain structures are formed above the upper surface of the semiconductor substrate. The first and second source/drain structures are laterally displaced over the first and second lightly doped regions of the semiconductor substrate.
摘要翻译：一种浅结MOS晶体管，包括具有上部区域的半导体衬底，所述上部区域包括在沟道区域的任一侧上横向移位的第一和第二轻掺杂区域。第一和第二轻掺杂区域延伸到半导体衬底的上表面下方的结深度。第一和第二轻掺杂杂质分布位于半导体衬底的第一和第二源极/漏极区域内。浅结晶体管还包括形成在半导体衬底的沟道区的上表面上的栅极电介质。包括第一和第二侧壁的导电栅极形成在栅极电介质上。栅极绝缘体形成为与导电栅极的第一和第二侧壁接触。第一和第二源极/漏极结构形成在半导体衬底的上表面之上。第一和第二源极/漏极结构在半导体衬底的第一和第二轻掺杂区域上横向移位。

35. 发明授权

US5955785A Copper-containing plug for connection of semiconductor surface with overlying conductor 失效
标题翻译：用于将半导体表面与上覆导体连接的含铜插头
公开(公告)号：US5955785A
公开(公告)日：1999-09-21
申请号：US13762
申请日：1998-01-27
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/485 , H01L23/532 , H01L29/43
CPC分类号： H01L23/485 , H01L21/76838 , H01L23/53238 , H01L2924/0002 , Y10S257/915
摘要： An integrated circuit fabrication process is provided in which copper is used as the contact plug material for a via. The via is a hole etched through an interlevel dielectric which is disposed upon a semiconductor topography, e.g., a silicon-based substrate having junctions therein. An inert implant may form an implant region within the semiconductor topography lying underneath the via. The process for forming the copper plug involves depositing a diffusion barrier upon the interlevel dielectric and within the via. Copper is then deposited via chemical vapor deposition upon the diffusion barrier such that the copper fills the entire via and forms a layer above the via. The copper is etched from all areas except from within the via, thereby forming a copper plug in the via. The resulting surface is then subjected to chemical-mechanical polishing before the diffusion barrier is removed from areas exclusive of the via. A conductive layer can be placed upon the interlevel dielectric and the copper plug to form a contact between the conductive layer and the semiconductor topography.
摘要翻译：提供了一种集成电路制造工艺，其中使用铜作为通孔的接触插塞材料。通孔是通过层间电介质蚀刻的孔，其布置在半导体形貌上，例如其中具有结的硅基衬底。惰性植入物可以在位于通孔下方的半导体形貌内形成植入区域。形成铜插塞的过程包括在层间电介质和通孔内沉积扩散阻挡层。然后通过化学气相沉积将铜沉积在扩散阻挡层上，使得铜填充整个通孔并形成通孔上方的层。从除了通孔内的所有区域蚀刻铜，从而在通孔中形成铜塞。然后将所得表面进行化学机械抛光，然后从不包括通孔的区域除去扩散阻挡层。可以将导电层放置在层间电介质和铜插塞上以形成导电层和半导体形貌之间的接触。

36. 发明授权

US5891793A Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation 失效
标题翻译：晶体管制造工艺采用公共室进行栅极氧化和栅极导体的形成
公开(公告)号：US5891793A
公开(公告)日：1999-04-06
申请号：US832943
申请日：1997-04-04
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： C23C16/40 , C23C16/452 , H01L21/28 , H01L21/314 , H01L29/51 , H01L21/3205
CPC分类号： H01L21/28202 , C23C16/402 , C23C16/452 , H01L21/28017 , H01L21/28035 , H01L21/3145 , H01L29/513 , H01L29/518 , H01L21/28185 , Y10S438/907 , Y10S438/908
摘要： An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber. The initial semiconductor topography includes a silicon substrate having isolation regions disposed within its upper surface. The semiconductor topography may include an defined region, or well, doped opposite the substrate. The semiconductor topography is first placed in the common chamber. A separate chamber is operably placed in gaseous communication with the common chamber. A plasma is created within the separate chamber, causing nitrogen, silicon, and oxygen containing compounds therein to form ions, molecular fragments, and excited molecules which are transported to the common chamber. The ions, molecular fragments, and excited molecules react and bombard the surface of the semiconductor topography to form an oxide layer thereon. The oxide layer is incorporated with nitrogen atoms which act as barrier atoms. Polysilicon is then deposited upon the oxide layer by CVD within the common chamber. The semiconductor topography is never exposed to ambient conditions outside the common chamber during and between the plasma oxide formation and the polysilicon deposition steps. Preventing ingress of outside ambient helps minimize contamination from entering the oxide. During the polysilicon deposition, dopant atoms are forwarded and become entrained within the polysilicon. The barrier atoms within the deposited oxide helps minimize dopant atoms from passing through the oxide and entering the channel below the oxide.
摘要翻译：提供了一种集成电路晶体管，其具有栅极氧化物和布置在半导体形貌上的栅极导体，栅极氧化物和栅极导体形成在公共室内。初始半导体形貌包括具有设置在其上表面内的隔离区的硅衬底。半导体形貌可以包括与衬底相对掺杂的限定区域或阱。首先将半导体形貌放置在公共室中。单独的室可操作地与公共室气体连通地放置。在分离的室内产生等离子体，在其中产生氮，硅和含氧化合物，以形成被输送到公共室的离子，分子片段和被激发的分子。离子，分子片段和激发的分子反应并轰击半导体形貌的表面以在其上形成氧化物层。氧化物层与作为阻挡原子的氮原子结合。然后通过CVD在公共室内将多晶硅沉积在氧化物层上。在等离子体氧化物形成和多晶硅沉积步骤期间和之间，半导体形貌从未暴露于公共室外的环境条件。防止外界进入有助于最大限度地减少进入氧化物的污染。在多晶硅沉积期间，掺杂剂原子被转移并被夹带在多晶硅内。沉积的氧化物内的阻挡原子有助于最小化掺杂剂原子通过氧化物并进入氧化物下方的通道。

37. 发明授权

US5882993A Integrated circuit with differing gate oxide thickness and process for making same 失效
标题翻译：具有不同栅极氧化物厚度的集成电路及其制造方法
公开(公告)号：US5882993A
公开(公告)日：1999-03-16
申请号：US699249
申请日：1996-08-19
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L27/088 , H01L21/316 , H01L21/8238 , H01L27/092 , H01L21/44 , H01L21/31
CPC分类号： H01L27/0922 , H01L21/823857 , Y10S438/981
摘要： A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon. Preferably, the step of introducing the nitrogen species impurity distribution into the semiconductor substrate is accomplished by thermally oxidizing the first substrate region in a nitrogen bearing ambient. In a presently preferred embodiment, the nitrogen bearing ambient includes N.sub.2 O, NH.sub.3, O.sub.2 and HCl in an approximate ratio of 60:30:7:3. In alternative embodiments the nitrogen bearing ambient includes NO, O.sub.2 and HCl in an approximate ratio of 90:7:3 or N.sub.2 O, O.sub.2 and HCl in an approximate ratio of 90:7:3. The introduction of the nitrogen species impurity into first substrate region 102 may alternatively be accomplished with rapid thermal anneal processing.
摘要翻译：一种用于在集成电路内产生两个栅极氧化物厚度的半导体工艺，其中提供具有第一区域和第二区域的半导体衬底。第一区域和第二区域相对于彼此横向移位。然后将氮物质杂质分布引入半导体衬底的第一区域。此后，在半导体衬底的上表面上生长栅极电介质层。栅极电介质在半导体衬底的第一区域上具有第一厚度，并且在半导体衬底的第二区域上具有第二厚度。第一厚度小于第二厚度。在本发明的CMOS实施例中，半导体衬底的第一区域包括p型硅，而第二衬底区域包括n型硅。优选地，将氮物质杂质分布引入半导体衬底的步骤是通过在含氮环境中热氧化第一衬底区域来实现的。在目前优选的实施方案中，含氮环境包括大约比例为60:30:7:3的N2O，NH3，O2和HCl。在替代实施方案中，含氮环境包括大约比例为90:7:3的N，O 2和HCl，N 2 O，O 2和HCl的比例大约为90:7:3。可以通过快速热退火处理来实现将氮物质杂质引入到第一衬底区域102中。

38. 发明授权

US5837572A CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein 失效
标题翻译： CMOS集成电路通过使用可移除间隔物在不对称PMOS结之间产生不对称的NMOS结形成，用于优化植入其中的掺杂剂的热扩散率
公开(公告)号：US5837572A
公开(公告)日：1998-11-17
申请号：US781461
申请日：1997-01-10
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/8238 , H01L21/82
CPC分类号： H01L21/823814 , H01L29/66659 , H01L29/7835
摘要： An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with pre-defined anneal temperatures applied after select implant steps. Both the NMOS and PMOS transistor junction are graded such that the drain areas include a relatively large LDD implant area and the source junctions do not. Whatever LDD area pre-existing in the source implanted with a higher concentration source/drain or MDD implant. The ensuing integrated circuit is therefore a CMOS circuit having asymmetrical transistor junctions and carefully controlled implant and anneal sequences. The asymmetrical junctions are retained, or at least optimized, by controlling the anneal temperatures such that diffusivity distances of n-type implants are relatively similar to p-type implants. Diffusivity is controlled by regulating the post-implant anneal temperatures of p-type implants lesser than previous n-type implants.
摘要翻译：提供具有NMOS晶体管和PMOS晶体管的集成电路。 NMOS晶体管结区优选地在具有预定义的退火温度的PMOS晶体管结区之后形成在选择的注入步骤之后。 NMOS和PMOS晶体管结都被分级，使得漏极区域包括相对较大的LDD注入区域，并且源极结不包括。无论在植入较高浓度源/漏或MDD植入物的源中预先存在LDD区域。因此，随后的集成电路是具有不对称晶体管结和仔细控制的注入和退火序列的CMOS电路。通过控制退火温度使得n型植入物的扩散距离相对于p型植入物保持或至少优化不对称结。通过调节比以前的n型植入物少的p型植入物的植入后退火温度来控制扩散性。

39. 发明授权

US5817560A Ultra short trench transistors and process for making same 失效
公开(公告)号：US5817560A
公开(公告)日：1998-10-06
申请号：US713281
申请日：1996-09-12
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66621 , H01L29/7834 , Y10S257/90
摘要： A field effect transistor comprising a semiconductor substrate having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench depth below an upper surface of the semiconductor substrate. The transistor further includes a gate dielectric layer that is formed on a floor of the transistor trench over a channel region of the semiconductor substrate. A conductive gate structure is formed above and in contact with the gate dielectric layer. A source/drain impurity distribution is formed within a source/drain region of the semiconductor substrate. The source/drain region is laterally disposed on either side of the channel region of the semiconductor substrate. In a preferred embodiment, the trench depth is between 1,000-5,000 angstroms and a thickness of the conductive gate structure is less than 5,000 angstroms such that an upper surface of the conductive gate structure is level with or below an upper surface of the semiconductor substrate. The gate dielectric layer suitably comprises a thermal oxide having a thickness of approximately 20-200 angstroms. In a lightly doped drain (LDD) embodiment, the source/drain impurity distribution includes a lightly doped region and a heavily doped region. The lightly doped region extends laterally from the channel region of the transistor to the heavily doped region. In the preferred embodiment, a lateral dimension of the channel region of the transistor is approximately 100-300 nm.

40. 发明授权

US5811347A Nitrogenated trench liner for improved shallow trench isolation 失效
标题翻译：氮化沟槽衬垫，用于改善浅沟槽隔离
公开(公告)号：US5811347A
公开(公告)日：1998-09-22
申请号：US641028
申请日：1996-04-29
申请人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
发明人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
IPC分类号： H01L21/314 , H01L21/318 , H01L21/762 , H01L21/76
CPC分类号： H01L21/3144 , H01L21/3185 , H01L21/76224 , Y10S148/05
摘要： A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner. Incorporation of nitrogen into the trench liner can be accomplished by either forming the trench liner in the presence of a nitrogen bearing ambient or by forming a pure SiO.sub.2 trench liner and subsequently implanting the SiO.sub.2 trench liner with nitrogen. After formation of the nitrogenated trench liner, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.
摘要翻译：一种在半导体衬底内的有源区之间形成改进的隔离沟槽的方法。改进的方法包括氮含量为约0.5至2.0％的沟槽衬垫。在硅衬底上形成衬垫层，并在衬垫层上形成氮化物层。此后，在氮化硅层上图案化光致抗蚀剂层，使得随后将形成隔离沟槽的氮化物层的区域被暴露。接下来，蚀刻掉位于氮化物层的暴露区域之下的氮化物层和焊盘层的暴露区域以暴露硅衬底的区域。随后，用干蚀刻工艺将隔离沟槽蚀刻到硅衬底中。然后形成沟槽衬垫，并且氮结合到沟槽衬里中。通过在存在氮气环境的情况下形成沟槽衬垫或通过形成纯的SiO 2沟槽衬垫并随后用氮气注入SiO 2沟槽衬垫，可以将氮掺入到沟槽衬里中。在形成氮化沟槽衬垫之后，用优选由CVD氧化物构成的电介质填充沟槽。此后，CVD填充电介质被平坦化，并且氮化物层被剥离。

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