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31. 发明申请

US20070023808A1 Semiconductor memory, the fabrication thereof and a method for operating the semiconductor memory 失效
标题翻译：半导体存储器，其制造和半导体存储器的操作方法
公开(公告)号：US20070023808A1
公开(公告)日：2007-02-01
申请号：US11193026
申请日：2005-07-29
申请人： Michael Specht , Wolfgang Roesner , Franz Hofmann
发明人： Michael Specht , Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L29/7887 , G11C16/0475 , H01L29/513 , H01L29/66833 , H01L29/7923
摘要： A semiconductor memory having a multitude of memory cells (21-1), the semiconductor memory having a substrate (1), at least one wordline (5-1), a first (15-1) and a second line (15-2; 16-1), wherein each of the multitude of memory cells (21-1) comprises a first doping region (6) disposed in the substrate (1), a second doping region (7) disposed in the substrate (1), a channel region (22) disposed in the substrate (1) between the first doping region (6) and the second doping region (7), a charge-trapping layer stack (2) disposed on the substrate (1), on the channel region (22), on a portion of the first doping region (6) and on a portion of the second doping region (7). Each memory cell (21-1) further comprises a conductive layer (3) disposed on the charge-trapping layer stack (2), wherein the conductive layer (3) is electrically floating. A dielectric layer (4) is disposed on a top surface of the conductive layer (3) and on sidewalls (23) of the conductive layer (3). The first line (15-1) extends along a first direction and is coupled to the first doping region (6), and the second line (15-2; 16-1) extends along the first direction and is coupled to the second doping region (7). The at least one wordline (5-1) extends along a second direction and is disposed on the dielectric layer (4).
摘要翻译：一种具有多个存储单元（21-1）的半导体存储器，所述半导体存储器具有衬底（1），至少一个字线（5-1），第一（15-1）和第二线（15-2） ; 16-1），其中多个存储单元（21-1）中的每一个包括设置在所述衬底（1）中的第一掺杂区域（6），设置在所述衬底（1）中的第二掺杂区域（7）设置在第一掺杂区域（6）和第二掺杂区域（7）之间的衬底（1）中的沟道区域（22），设置在衬底（1）上的电荷捕获层堆叠（2）在第一掺杂区域（6）的一部分上和第二掺杂区域（7）的一部分上的区域（22）。每个存储单元（21-1）还包括设置在电荷捕获层堆叠（2）上的导电层（3），其中导电层（3）是电浮置的。介电层（4）设置在导电层（3）的顶表面和导电层（3）的侧壁（23）上。第一线（15-1）沿着第一方向延伸并且耦合到第一掺杂区域（6），并且第二线路（15-2; 16-1）沿着第一方向延伸并且耦合到第二掺杂地区（7）。所述至少一个字线（5-1）沿着第二方向延伸并且设置在所述电介质层（4）上。

32. 发明申请

US20070018201A1 Non-volatile memory cells and methods for fabricating non-volatile memory cells 有权
标题翻译：非易失性存储单元和用于制造非易失性存储单元的方法
公开(公告)号：US20070018201A1
公开(公告)日：2007-01-25
申请号：US11187693
申请日：2005-07-22
申请人： Michael Specht , Franz Hofmann , Johannes Luyken
发明人： Michael Specht , Franz Hofmann , Johannes Luyken
IPC分类号： H01L27/10
CPC分类号： H01L27/11568 , H01L21/84 , H01L27/115 , H01L27/1203 , H01L29/785
摘要： The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a bulk semi-conductive substrate and an SOI semi-conductive layer and are arranged as a bulk FinFET transistor and an SOI FinFet transistor being arranged on top of the bulk FinFET transistor. Both the FinFET transistor and the SOI FinFet transistor are attached to a common charge-trapping layer. A word line with sidewalls is arranged on top of said patterned charge-trapping layer and a spacer oxide layer is arranged on the sidewalls of said word line.
摘要翻译：本发明涉及一种用于制造堆叠的非易失性存储单元的方法。此外，本发明涉及堆叠的非易失性存储单元。本发明特别涉及具有非易失性堆叠存储单元的非易失性NAND存储器的领域。层叠的非易失性存储单元形成在具有体半导体基板和SOI半导电层的半导体晶片上，并且被布置为体FinFET晶体管，并且SOI FinFet晶体管布置在体FinFET晶体管的顶部。 FinFET晶体管和SOI FinFet晶体管都连接到公共的电荷俘获层。具有侧壁的字线被布置在所述图案化的电荷捕获层的顶部上，并且间隔氧化物层被布置在所述字线的侧壁上。

33. 发明申请

US20060261403A1 Semiconductor memory device and method of production 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20060261403A1
公开(公告)日：2006-11-23
申请号：US11135002
申请日：2005-05-23
申请人： Franz Hofmann , Johannes Luyken , Michael Specht
发明人： Franz Hofmann , Johannes Luyken , Michael Specht
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4232 , H01L29/42352 , H01L29/66833
摘要： An array of charge-trapping memory cells and pluralities of parallel wordlines and parallel bitlines running transversely to the wordlines are arranged on a substrate surface. Gate electrodes are located between the wordlines and bitlines and are, in their sequence along the direction of the wordlines, connected alternatingly to one of two adjacent wordlines.
摘要翻译：电荷俘获存储器单元阵列和横向于字线的并行字线和并行位线的多个排列在衬底表面上。栅电极位于字线和位线之间，并且沿着字线方向的顺序交替地连接到两个相邻字线之一。

34. 发明申请

US20060181925A1 Nonvolatile memory cell arrangement 有权
标题翻译：非易失性存储单元布置
公开(公告)号：US20060181925A1
公开(公告)日：2006-08-17
申请号：US11283572
申请日：2005-11-18
申请人： Michael Specht , Franz Hofmann , Ulrich Dorda , Johannes Kretz , Lars Dreeskornfeld
发明人： Michael Specht , Franz Hofmann , Ulrich Dorda , Johannes Kretz , Lars Dreeskornfeld
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0466 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.
摘要翻译：存储晶体管被布置成多个行和列。第一列的每个存储晶体管的第一源极/漏极端子连接到第一金属化平面中的导电导体轨道，并且与第一列相邻的第二列的每个存储晶体管的第一源极/漏极端子被连接到第二金属化平面中的导电导体轨道。

35. 发明申请

US20050269617A1 Semi-conductor component with condensators buried in the substrate and insulated component layer thereof 有权
标题翻译：半导体部件与冷凝器埋在基板和绝缘部件层中
公开(公告)号：US20050269617A1
公开(公告)日：2005-12-08
申请号：US10523944
申请日：2003-09-13
申请人： Franz Hofmann , Volker Lehmann , Lothar Risoh , Wolfgang Rosner , Michael Specht
发明人： Franz Hofmann , Volker Lehmann , Lothar Risoh , Wolfgang Rosner , Michael Specht
IPC分类号： H01L21/02 , H01L21/334 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/94 , H01L29/76
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10832 , H01L27/10867 , H01L27/1203 , H01L28/82 , H01L29/66181 , H01L29/945
摘要： A semiconductor substrate and a semiconductor circuit formed therein and associated fabrication methods are provided. A multiplicity of depressions with a respective dielectric layer and a capacitor electrode are formed for realizing buried capacitors in a carrier substrate and an actual semiconductor component layer being insulated from the carrier substrate by an insulation layer.
摘要翻译：提供了一种形成在其中的半导体衬底和半导体电路及其制造方法。形成具有相应电介质层和电容器电极的多个凹陷，用于在载体衬底中实现埋入式电容器，并且通过绝缘层与实施方式的半导体组件层与载体衬底绝缘。

36. 发明申请

US20050199913A1 Word and bit line arrangement for a FinFET semiconductor memory 审中-公开
标题翻译：用于FinFET半导体存储器的字和位线布置
公开(公告)号：US20050199913A1
公开(公告)日：2005-09-15
申请号：US11074345
申请日：2005-03-07
申请人： Franz Hofmann , Thomas Schulz , Michael Specht
发明人： Franz Hofmann , Thomas Schulz , Michael Specht
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： The invention relates to a semiconductor memory having a multiplicity of fins made of semiconductor material which are spaced apart from one another, a multiplicity of channel regions and contact regions being formed in each of the fins, a multiplicity of word lines, a multiplicity of storage layers, at least one of the storage layers being arranged between each of the channel regions and the word line, and a multiplicity of bit lines, the longitudinal axes of first bit line portions running parallel to a first bit line direction and the longitudinal axes of second bit line portions running parallel to a second bit line direction, the second bit line direction being rotated relative to the first bit line direction, each of the bit lines being electrically connected to a multiplicity of the contact regions, wherein, between two contact regions of the same fin that are connected to one of the bit lines, a contact region is not connected to the respective bit line.
摘要翻译：本发明涉及一种半导体存储器，其具有由半导体材料制成的多个鳍片，它们彼此间隔开，多个通道区域和接触区域形成在每个鳍片中，多个字线，多个存储器存储层中的至少一个布置在每个沟道区域和字线之间，并且多个位线，第一位线部分的纵向轴线平行于第一位线方向延伸，并且纵向轴线第二位线部分平行于第二位线方向延伸，第二位线方向相对于第一位线方向旋转，每个位线电连接到多个接触区域，其中在两个接触区域之间与位线之一连接的相同的鳍片，接触区域不连接到相应的位线。

37. 发明申请

US20050139893A1 Non-volatile flash semiconductor memory and fabrication method 有权
标题翻译：非易失性闪存半导体存储器及其制造方法
公开(公告)号：US20050139893A1
公开(公告)日：2005-06-30
申请号：US10991345
申请日：2004-11-09
申请人： Franz Hofmann , Erhard Landgraf , Wolfgang Rosner , Michael Specht , Martin Staedele
发明人： Franz Hofmann , Erhard Landgraf , Wolfgang Rosner , Michael Specht , Martin Staedele
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L21/8242 , H01L29/76
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the fins, in order to form side wall transistors, and between the gate electrodes forms parts of a word line belonging to the corresponding fin.
摘要翻译：在半导体存储器中，在由半导体材料制成的翅片的相应顶侧上存在多个具有捕获层或浮栅电极作为存储介质的FinFET布置。栅电极的材料也存在于翅片的两个侧壁上，以便形成侧壁晶体管，并且在栅电极之间形成属于相应鳍片的字线的部分。

38. 发明申请

US20050048720A1 Floating gate memory cell, floating gate memory arrangement circuit arrangement and method for fabricating a floating gate memory cell 有权
标题翻译：浮栅存储器单元，浮栅存储器布置电路布置和制造浮栅存储单元的方法
公开(公告)号：US20050048720A1
公开(公告)日：2005-03-03
申请号：US10926838
申请日：2004-08-25
申请人： Andrew Graham , Franz Hofmann , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Michael Specht
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11519 , H01L21/28273 , H01L27/11521 , H01L27/11551 , H01L29/66825
摘要： Floating gate memory cell having a first layer with first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions, and a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material.
摘要翻译：具有具有第一和第二源极/漏极区域的第一层和布置在第一和第二源极/漏极区域之间和之后的沟道区域的浮动栅极存储单元以及布置在第一层上的浮动栅极层，其中第一和第二源极/漏极区域和浮置栅极层由金属导电材料形成，并且沟道区域由电绝缘材料形成。

39. 发明授权

US08097915B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08097915B2
公开(公告)日：2012-01-17
申请号：US11139976
申请日：2005-05-31
申请人： Wolfgang Rösner , Franz Hofmann , Michael Specht , Martin Städele , Johannes Luyken
发明人： Wolfgang Rösner , Franz Hofmann , Michael Specht , Martin Städele , Johannes Luyken
IPC分类号： H01L31/119
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7393
摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.
摘要翻译：半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极具有栅极电介质层和栅电极的结构。所述栅极结构布置在所述漏极区域和所述源极区域之间。提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。

40. 发明授权

US07915667B2 Integrated circuits having a contact region and methods for manufacturing the same 有权
标题翻译：具有接触区域的集成电路及其制造方法
公开(公告)号：US07915667B2
公开(公告)日：2011-03-29
申请号：US12137388
申请日：2008-06-11
申请人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
发明人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
IPC分类号： H01L29/792 , H01L29/788 , H01L21/336
CPC分类号： H01L21/28282 , H01L21/28273 , H01L21/8221 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
摘要翻译：在一个实施例中，提供了具有存储单元布置的集成电路。存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移基材的主要加工表面。

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