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31. 发明授权

US07336667B2 Apparatus, method and program product to generate and use CRC in communications network 有权
标题翻译：在通信网络中生成和使用CRC的装置，方法和程序产品
公开(公告)号：US07336667B2
公开(公告)日：2008-02-26
申请号：US10301247
申请日：2002-11-21
申请人： James J. Allen, Jr. , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice J. Verplanken
发明人： James J. Allen, Jr. , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice J. Verplanken
IPC分类号： H04L12/28 , H03M13/00
CPC分类号： H04L1/0061 , H04L1/0072 , H04L12/5601 , H04L45/742 , H04L2012/5627 , H04L2012/5656
摘要： The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 216 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, Li field and UUI field with the two tables.
摘要翻译：用于ATM AAL2单元的CPS头的CRC由CRC发生器产生，CRC发生器使用CID字段的8位来产生加载在第一表中的部分5位CRC。 6位LI字段和5位UUI字段被添加到部分5位CRC以形成16位。 CRC发生器使用2位16位产生第二个CRC表。通过将CID字段，Li字段和UUI字段中的比特与两个表相关来生成特定CPS头的CRC。

32. 发明授权

US08122132B2 Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information 有权
标题翻译：基于广播信息将作业动态地分配给集群中的处理器的技术
公开(公告)号：US08122132B2
公开(公告)日：2012-02-21
申请号：US12336312
申请日：2008-12-16
申请人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
发明人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
IPC分类号： G06F13/00
CPC分类号： G06F9/5088
摘要： A technique for operating a high performance computing cluster (HPC) having multiple nodes (each of which include multiple processors) includes periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes. Respective local job tables maintained in each of the multiple nodes are updated based on the broadcast information. One or more threads are then moved from one or more of the multiple processors to a different one of the multiple processors (based on the broadcast information in the respective local job tables).
摘要翻译：用于操作具有多个节点（每个包括多个处理器）的高性能计算群集（HPC）的技术包括：从多个节点中的每个节点到多个节点周期性地广播与多个节点中的每个节点处的处理器利用和网络利用相关的信息多个节点中的一个。基于广播信息来更新维护在多个节点中的每个节点的相应的本地作业表。然后，一个或多个线程从多个处理器中的一个或多个移动到多个处理器中的不同处理器（基于相应的本地作业表中的广播信息）。

33. 发明授权

US07929438B2 Scheduler pipeline design for hierarchical link sharing 失效
标题翻译：调度器管道设计用于分层链路共享
公开(公告)号：US07929438B2
公开(公告)日：2011-04-19
申请号：US12175479
申请日：2008-07-18
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04J1/16
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

34. 发明授权

US07844746B2 Accessing an effective address and determining whether the effective address is associated with remotely coupled I/O adapters 有权
标题翻译：访问有效地址并确定有效地址是否与远程耦合的I / O适配器相关联
公开(公告)号：US07844746B2
公开(公告)日：2010-11-30
申请号：US12024695
申请日：2008-02-01
申请人： Ravi K. Arimilli , Claude Basso , Jean L. Calvignac , Edward J. Seminaro
发明人： Ravi K. Arimilli , Claude Basso , Jean L. Calvignac , Edward J. Seminaro
IPC分类号： G06F3/12
CPC分类号： G06F9/45558 , G06F2009/45579
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model abstracts an I/O device such that communication intended for the I/O device may be packetized and sent over a network. Thus, a virtualization platform may packetize communication intended for a remotely located I/O device and transmit the packetized communication over a distance, rather than having to make a call to a library, call a device driver, pin memory, and so forth.
摘要翻译：提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于例。异构处理元件模型抽象出I / O设备，使得针对I / O设备的通信可以被分组并通过网络发送。因此，虚拟化平台可以打包用于远程位置的I / O设备的通信，并且在一定距离上发送分组化的通信，而不是必须对库进行呼叫，调用设备驱动器，引脚存储器等。

35. 发明申请

US20100153541A1 TECHNIQUES FOR DYNAMICALLY ASSIGNING JOBS TO PROCESSORS IN A CLUSTER BASED ON PROCESSOR WORKLOAD 有权
标题翻译：基于处理器工作负载的集群中的处理器动态组织工作的技术
公开(公告)号：US20100153541A1
公开(公告)日：2010-06-17
申请号：US12336256
申请日：2008-12-16
申请人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
发明人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
IPC分类号： G06F15/173
CPC分类号： G06F9/5088
摘要： A technique for operating a high performance computing (HPC) cluster includes monitoring workloads of multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more threads assigned to one or more of the multiple processors are moved to a different one of the multiple processors based on the workloads of the multiple processors.
摘要翻译：用于操作高性能计算（HPC）集群的技术包括监视包含在HPC集群中的多个处理器的工作负载。 HPC集群包括多个节点，每个节点包含多个处理器中的两个或多个。基于多个处理器的工作负载，分配给多个处理器中的一个或多个的一个或多个线程被移动到多个处理器中的不同处理器。

36. 发明授权

US07643511B2 Frame alteration logic for network processors 失效
标题翻译：网络处理器的帧更改逻辑
公开(公告)号：US07643511B2
公开(公告)日：2010-01-05
申请号：US12327761
申请日：2008-12-03
申请人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Valdhyanathan , Johan G. A. Verkinderen
发明人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Valdhyanathan , Johan G. A. Verkinderen
IPC分类号： H04J3/22
CPC分类号： H04L49/25 , H04L49/3009 , H04L49/40
摘要： Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.
摘要翻译：通信系统中的分组交换节点包括用于接收具有格式化控制块的包含报头部分的输入信息分组或帧的装置。帧头中的信息包含用于修改帧中的信息的帧改变命令。修改包括添加新信息，删除信息和叠加信息。变更引擎中的解码器和控制装置解释命令并对帧数据应用修改。存储通用和标准数据模式用于插入或覆盖以节省数据分组空间。

37. 发明申请

US20090097404A1 Oversubscribing Bandwidth In A Communications Network 有权
标题翻译：在通信网络中超频带宽
公开(公告)号：US20090097404A1
公开(公告)日：2009-04-16
申请号：US12272711
申请日：2008-11-17
申请人： Philippe Damon , Claude Basso , Jean L. Calvignac , Francis Arts , Pierre L. Debuysscher
发明人： Philippe Damon , Claude Basso , Jean L. Calvignac , Francis Arts , Pierre L. Debuysscher
IPC分类号： H04L12/24 , G01R31/08
CPC分类号： H04L47/10 , H04L47/20
摘要： A system and computer readable medium for oversubscribing bandwidth in a communication network, is disclosed. The system and computer readable medium includes policing a first data flow and outputting a first output data flow from the first meter, in relation to a first Committed Information Rate (CIR) and a first Peak Information Rate (PIR); policing a second data flow and outputting a second output data flow from the second meter in relation to a second CIR and a second PIR; and policing an aggregated output data flow of the first output data flow and the second output data through a third meter of the oversubscription module, where the aggregated output data flow is policed in relation to a third CIR and a third PIR.
摘要翻译：公开了一种在通信网络中超额订购带宽的系统和计算机可读介质。系统和计算机可读介质包括对第一数据流进行管理，并相对于第一承诺信息速率（CIR）和第一峰值信息速率（PIR）从第一仪表输出第一输出数据流; 管理第二数据流，并相对于第二CIR和第二PIR从第二计量器输出第二输出数据流; 以及通过所述超额预订模块的第三计量管理所述第一输出数据流和所述第二输出数据的聚合输出数据流，其中所述聚合输出数据流相对于第三CIR和第三PIR进行监管。

38. 发明授权

US07457241B2 Structure for scheduler pipeline design for hierarchical link sharing 失效
标题翻译：用于分层链路共享的调度器流水线设计的结构
公开(公告)号：US07457241B2
公开(公告)日：2008-11-25
申请号：US10772737
申请日：2004-02-05
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04J1/16
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

39. 发明授权

US07406080B2 Method and structure for enqueuing data packets for processing 失效
标题翻译：排队处理数据包的方法和结构
公开(公告)号：US07406080B2
公开(公告)日：2008-07-29
申请号：US10868725
申请日：2004-06-15
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L49/9042 , H04L49/9073 , H04L69/22
摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.
摘要翻译：提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。该方法包括利用报头信息来识别分组的其余部分的位置和范围。当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时有空间。

40. 发明授权

US08959224B2 Network data packet processing 有权
标题翻译：网络数据包处理
公开(公告)号：US08959224B2
公开(公告)日：2015-02-17
申请号：US13299045
申请日：2011-11-17
申请人： Claude Basso , Jean L. Calvignac , Hubertus Franke , Eren Kursun
发明人： Claude Basso , Jean L. Calvignac , Hubertus Franke , Eren Kursun
IPC分类号： G06F15/173 , G06F9/46 , G06F1/32 , G06F9/50
CPC分类号： G06F1/3209 , G06F9/5094 , Y02D10/22
摘要： A method and apparatus for processing of data packets by a data processing component comprising a plurality of processing resources. A metric value for a current configuration of the processing resources that are processing the data packets is identified. A new configuration of the processing resources is selected using the metric value. The current configuration of the processing resources is changed to the new configuration and data packets are distributed to the new configuration for processing as the data packets are received.
摘要翻译：一种由包括多个处理资源的数据处理组件处理数据分组的方法和装置。识别处理数据分组的处理资源的当前配置的度量值。使用度量值选择处理资源的新配置。处理资源的当前配置被改变为新的配置，并且数据分组被分配到新配置，以便在接收到数据分组时进行处理。

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