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    • 36. 发明授权
    • Self aligned vias in dual damascene interconnect, buried mask approach
    • 双镶嵌互连中的自对准通孔,掩埋掩模法
    • US06911389B2
    • 2005-06-28
    • US10246061
    • 2002-09-18
    • Kenneth D. BrennanPaul Gillespie
    • Kenneth D. BrennanPaul Gillespie
    • H01L21/768H01L23/522H01L21/44
    • H01L21/7681H01L23/5226H01L2924/0002H01L2924/00
    • Methods are disclosed for forming vias, trenches, and interconnects through diffusion barrier, etch-stop, and dielectric materials for interconnection of electrical devices in dual damascene structures of a semiconductor device. A buried via mask at the etch-stop level provides openings with two or more adjacent via misalignment error regions merged into rectangular windows aligned orthogonal to a long axis of the underlying conductive features of a first metal level. The rectangular windows used together with openings in a hard mask form via portions, and the openings in the hard mask provide trench portions. Via and trench portions coincide during trench or via etch, as well as during hard mask or etch-stop layer etch together forming an interconnect cavity, which may then be filled with a conductive material to provide a conductive interconnect between the conductive feature of the first metal level and a second metal level.
    • 公开了用于通过扩散屏障,蚀刻停止和介电材料形成通孔,沟槽和互连的方法,用于半导体器件的双镶嵌结构中的电器件的互连。 在蚀刻停止水平处的掩埋通孔掩模提供具有两个或更多个相邻的通孔未对准误差区域的开口,该相邻的通孔未对准误差区域被合并成与第一金属水平的底部导电特征的长轴正交排列的矩形窗口。 与通过部分的硬掩模形式的开口一起使用的矩形窗口,并且硬掩模中的开口提供沟槽部分。 通孔和沟槽部分在沟槽或通孔蚀刻期间重合,以及在硬掩模或蚀刻停止层蚀刻期间一起形成互连腔,然后可以用导电材料填充以在第一和第二导电特征之间提供导电互连 金属水平和第二金属水平。