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31. 发明授权

US08106380B2 Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same 有权
标题翻译：使用具有限定杂质梯度的应变材料层的半导体结构及其制造方法
公开(公告)号：US08106380B2
公开(公告)日：2012-01-31
申请号：US12982101
申请日：2010-12-30
申请人： Matthew T. Currie , Anthony J. Lochtefeld , Richard Hammond , Eugene Fitzgerald
发明人： Matthew T. Currie , Anthony J. Lochtefeld , Richard Hammond , Eugene Fitzgerald
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L29/105 , H01L29/161 , H01L29/36 , H01L29/66477 , H01L29/66545 , H01L29/66651 , H01L29/78 , H01L29/7842 , Y10S438/926
摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
摘要翻译：包括具有无杂质区域的应变材料层的半导体结构和器件及其制造方法。应变材料层的某些区域保持没有可以从半导体的相邻部分相互扩散的杂质。当杂质存在于应变材料层的某些区域中时，器件性能下降。通过采用具有所描述的或者根据所描述的步骤制造的特征的半导体结构和器件（例如，场效应晶体管或“FET”），器件操作被增强。

32. 发明申请

US20070293003A1 SEMICONDUCTOR STRUCTURES EMPLOYING STRAINED MATERIAL LAYERS WITH DEFINED IMPURITY GRADIENTS AND METHODS FOR FABRICATING SAME 有权
公开(公告)号：US20070293003A1
公开(公告)日：2007-12-20
申请号：US11847721
申请日：2007-08-30
申请人： Matthew Currie , Anthony Lochtefeld , Richard Hammond , Eugene Fitzgerald
发明人： Matthew Currie , Anthony Lochtefeld , Richard Hammond , Eugene Fitzgerald
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/105 , H01L29/161 , H01L29/36 , H01L29/66477 , H01L29/66545 , H01L29/66651 , H01L29/78 , H01L29/7842 , Y10S438/926
摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

33. 发明授权

US07259108B2 Methods for fabricating strained layers on semiconductor substrates 有权
标题翻译：在半导体衬底上制造应变层的方法
公开(公告)号：US07259108B2
公开(公告)日：2007-08-21
申请号：US11362892
申请日：2006-02-27
申请人： Eugene Fitzgerald , Matthew Currie
发明人： Eugene Fitzgerald , Matthew Currie
IPC分类号： H01L21/31
CPC分类号： C30B29/52 , C30B25/02 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/2205
摘要： Methods for fabricating multi-layer semiconductor structures including strained material layers using a minimum number of process tools and under conditions optimized for each layer. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
摘要翻译：制造多层半导体结构的方法，包括使用最少数量的工艺工具和在每个层优化的条件下的应变材料层。应变材料层的某些区域保持没有可以从半导体的相邻部分相互扩散的杂质。当杂质存在于应变材料层的某些区域中时，器件性能下降。通过采用具有所描述或者根据所描述的步骤制造的特征的半导体结构和器件（例如，场效应晶体管或“FET”），器件操作被增强。

34. 发明申请

US20070105274A1 Monolithically integrated semiconductor materials and devices 有权
标题翻译：单片集成半导体材料和器件
公开(公告)号：US20070105274A1
公开(公告)日：2007-05-10
申请号：US11591333
申请日：2006-11-01
申请人： Eugene Fitzgerald
发明人： Eugene Fitzgerald
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L27/14601 , H01L21/0245 , H01L21/0251 , H01L21/76254 , H01L21/8258 , H01L27/0605 , H01L27/144 , H01L27/1446 , H01L27/14683 , H01L27/15 , H01L27/156 , H01L31/0328 , H01L31/143 , H01L31/162 , H01L2924/0002 , Y10S438/933 , H01L2924/00
摘要： Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a semiconductor structure includes a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The semiconductor structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region, a monocrystalline silicon layer disposed over the insulating layer in the first region, and a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region. The second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon.
摘要翻译：提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。在一种结构中，半导体结构包括硅衬底和设置在硅衬底上的第一单晶半导体层，其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。半导体结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层，设置在第一区域中的绝缘层上的单晶硅层和设置在第一单晶的至少一部分上的第二单晶半导体层半导体层在第二区域中并且不存在于第一区域中。第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。

35. 发明申请

US20070082470A1 Gate technology for strained surface channel and strained buried channel MOSFET devices 审中-公开
公开(公告)号：US20070082470A1
公开(公告)日：2007-04-12
申请号：US11520175
申请日：2006-09-13
申请人： Eugene Fitzgerald , Richard Hammond , Matthew Currie
发明人： Eugene Fitzgerald , Richard Hammond , Matthew Currie
IPC分类号： H01L21/3205 , H01L21/28
CPC分类号： H01L29/66477 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/28194 , H01L21/28211 , H01L21/28238 , H01L29/1054 , H01L29/78 , H01L29/7838 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1−xGex layer on a substrate, a strained channel layer on the relaxed Si1−xGex layer, and a Si1−yGey layer; removing the Si1−yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

36. 发明申请

US20070032009A1 Semiconductor devices having strained dual channel layers 有权
标题翻译：具有应变双通道层的半导体器件
公开(公告)号：US20070032009A1
公开(公告)日：2007-02-08
申请号：US11544245
申请日：2006-10-06
申请人： Matthew Currie , Anthony Lochtefeld , Christopher Leitz , Eugene Fitzgerald
发明人： Matthew Currie , Anthony Lochtefeld , Christopher Leitz , Eugene Fitzgerald
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66628 , H01L29/66636 , H01L29/66651 , H01L29/66916 , H01L29/802 , Y10S438/938
摘要： A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.
摘要翻译：半导体结构包括锗浓度为至少10原子％的应变诱导基底层。半导体结构还包括在应变诱导基底层上的压缩应变层。压缩应变层的锗浓度比应变诱导基底层的锗浓度大至少约30个百分点，并且具有小于其临界厚度的厚度。半导体结构还包括在压缩应变层上的拉伸应变层。拉伸应变层可以由厚度小于其临界厚度的硅形成。一种用于制造半导体结构的方法包括：提供衬底，在衬底上提供压缩应变半导体，在衬底附近沉积拉伸应变半导体，直到拉伸应变半导体的第一区域的厚度大于第二区域的厚度的拉伸应变半导体，在第一区域上形成n沟道器件，并在第二区域上形成p沟道器件。

37. 发明申请

US20060197123A1 Methods for forming strained-semiconductor-on-insulator bipolar device structures 审中-公开
标题翻译：用于形成应变半导体绝缘体上双极器件结构的方法
公开(公告)号：US20060197123A1
公开(公告)日：2006-09-07
申请号：US11415556
申请日：2006-05-01
申请人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Glyn Braithwaite , Eugene Fitzgerald
发明人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Glyn Braithwaite , Eugene Fitzgerald
IPC分类号： H01L21/8234 , H01L29/76 , H01L31/00
CPC分类号： H01L29/785 , H01L21/76254 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/66795 , H01L29/66916 , H01L29/7842 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

38. 发明申请

US20060186510A1 Strained-semiconductor-on-insulator bipolar device structures 审中-公开
标题翻译：应变半导体绝缘体上双极器件结构
公开(公告)号：US20060186510A1
公开(公告)日：2006-08-24
申请号：US11412276
申请日：2006-04-27
申请人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Glyn Braithwaite , Eugene Fitzgerald
发明人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Glyn Braithwaite , Eugene Fitzgerald
IPC分类号： H01L29/73
CPC分类号： H01L29/785 , H01L21/76254 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/66795 , H01L29/66916 , H01L29/7842 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

39. 发明授权

US06831292B2 Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same 有权
标题翻译：使用具有限定杂质梯度的应变材料层的半导体结构及其制造方法
公开(公告)号：US06831292B2
公开(公告)日：2004-12-14
申请号：US10251424
申请日：2002-09-20
申请人： Matthew Currie , Anthony Lochtefeld , Richard Hammond , Eugene Fitzgerald
发明人： Matthew Currie , Anthony Lochtefeld , Richard Hammond , Eugene Fitzgerald
IPC分类号： H01L2906
CPC分类号： H01L29/1054 , H01L29/105 , H01L29/161 , H01L29/36 , H01L29/66477 , H01L29/66545 , H01L29/66651 , H01L29/78 , H01L29/7842 , Y10S438/926
摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
摘要翻译：包括具有无杂质区域的应变材料层的半导体结构和器件及其制造方法。应变材料层的某些区域保持没有可以从半导体的相邻部分相互扩散的杂质。当杂质存在于应变材料层的某些区域中时，器件性能下降。通过采用具有所描述或者根据所描述的步骤制造的特征的半导体结构和器件（例如，场效应晶体管或“FET”），器件操作被增强。

40. 发明申请

US20070105335A1 Monolithically integrated silicon and III-V electronics 有权
标题翻译：单片集成硅和III-V电子元件
公开(公告)号：US20070105335A1
公开(公告)日：2007-05-10
申请号：US11591383
申请日：2006-11-01
申请人： Eugene Fitzgerald
发明人： Eugene Fitzgerald
IPC分类号： H01L31/113 , H01L21/76
CPC分类号： H01L27/14601 , H01L21/0245 , H01L21/0251 , H01L21/76254 , H01L21/8258 , H01L27/0605 , H01L27/144 , H01L27/1446 , H01L27/14683 , H01L27/15 , H01L27/156 , H01L31/0328 , H01L31/143 , H01L31/162 , H01L2924/0002 , Y10S438/933 , H01L2924/00
摘要： Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure also includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device comprising an element including at least a portion of the monocrystalline silicon layer. The structure includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure also includes at least one III-V electronic device comprising an element including at least a portion of the second monocrystalline semiconductor layer.
摘要翻译：提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。在一种结构中，单片集成半导体器件结构包括硅衬底和设置在硅衬底上的第一单晶半导体层，其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。该结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层和设置在第一区域中的绝缘层上的单晶硅层。该结构包括至少一个硅基电子器件，其包含至少部分单晶硅层的元件。该结构包括第二单晶半导体层，其设置在第二区域中的第一单晶半导体层的至少一部分上且不存在于第一区域中，其中第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。该结构还包括至少一个III-V电子器件，其包括包含第二单晶半导体层的至少一部分的元件。

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