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31. 发明申请

US20090224316A1 Power MOS device with conductive contact layer 有权
标题翻译：功率MOS器件具有导电接触层
公开(公告)号：US20090224316A1
公开(公告)日：2009-09-10
申请号：US12384172
申请日：2009-03-31
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/772
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device includes a drain, a body disposed over the drain, a source embedded in the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench extending through the source into the body, a conductive contact layer disposed along at least a portion of a source body contact trench sidewall and in contact with at least a portion of the source, and a trench filling material disposed in the source body contact trench and overlaying at least a portion of the conductive contact layer.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，嵌入在主体中的源极，通过源极和主体延伸到漏极中的栅极沟槽，设置在栅极沟槽中的栅极，源体接触沟槽延伸穿过源体进入体内，导电接触层沿着源体接触沟槽侧壁的至少一部分设置并与源的至少一部分接触，以及沟槽填充材料，其设置在源体接触沟槽中并覆盖在至少一部分导电接触层。

32. 发明申请

US20090148995A1 Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) 有权
标题翻译：用于制造具有过多圆形屏蔽栅极沟槽（SGT）的MOSFET器件的工艺
公开(公告)号：US20090148995A1
公开(公告)日：2009-06-11
申请号：US12378040
申请日：2009-02-09
申请人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
发明人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
IPC分类号： H01L21/336
CPC分类号： H01L21/76232 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/7834
摘要： This invention discloses an improved method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) device. The method includes a step of opening a trench in substrate and covering trench walls of the trench with a linen layer followed by removing a portion of the linen layer from a bottom portion of the trench. The method further includes a step of opening a round hole by applying an isotropic substrate etch on the bottom portion of the trench with the round hole extending laterally from the trench walls. The method further includes a step of filling the trench and the round hole at the bottom of the trench with a gate material followed by applying a time etch to removed the gate material from a top portion of the trench whereby the gate material only filling the round hole up to a lateral expansion point of the round hole.
摘要翻译：本发明公开了一种用于制造沟槽金属氧化物半导体场效应晶体管（MOSFET）器件的改进方法。该方法包括在衬底中打开沟槽并且用亚麻层覆盖沟槽的沟槽壁，然后从沟槽的底部去除一部分亚麻层的步骤。该方法还包括通过在沟槽的底部施加各向同性的基底蚀刻来打开圆孔的步骤，其中圆形孔从沟槽壁横向延伸。该方法还包括用栅极材料填充沟槽底部的沟槽和圆孔，然后施加时间蚀刻以从沟槽的顶部去除栅极材料的步骤，由此栅极材料仅填充圆形孔直到圆孔的侧向膨胀点。

33. 发明申请

US20080233748A1 ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY 有权
标题翻译： SGT技术的ETCH深度测定
公开(公告)号：US20080233748A1
公开(公告)日：2008-09-25
申请号：US11690546
申请日：2007-03-23
申请人： Yingying Lou , Tiesheng Li , Yu Wang , Anup Bhalla
发明人： Yingying Lou , Tiesheng Li , Yu Wang , Anup Bhalla
IPC分类号： C23F1/00 , H01L21/302
CPC分类号： H01L22/12 , H01L29/407 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the layer of material. The resist mask does not cover the trench. The layer of material is isotropically etched. An etch depth may be determined from a characteristic of etching of the material underneath the mask. Such a method may be used for forming SGT structures. The wafer may comprise a layer of material disposed on at least a portion of a surface of semiconductor wafer; a resist mask comprising an angle-shaped test portion disposed over a portion of the layer of material; and a ruler marking on the surface of the substrate proximate the test portion.
摘要翻译：公开了一种用于确定深度蚀刻的方法，形成屏蔽栅沟槽（SGT）结构的方法和半导体器件晶片。在具有沟槽的衬底的一部分上形成材料层。材料填充沟槽。抗蚀剂掩模放置在材料层的测试部分上。抗蚀剂掩模不覆盖沟槽。材料层被各向同性地蚀刻。可以根据掩模下面的材料的蚀刻特性确定蚀刻深度。这种方法可用于形成SGT结构。晶片可以包括设置在半导体晶片的表面的至少一部分上的材料层; 抗蚀剂掩模，其包括设置在所述材料层的一部分上的角形测试部分; 以及在靠近测试部分的基板的表面上标记的标尺。

34. 发明申请

US20060180855A1 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US20060180855A1
公开(公告)日：2006-08-17
申请号：US11056346
申请日：2005-02-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成栅极沟槽，通过硬掩模，在栅极沟槽中沉积栅极材料，去除硬掩模以留下栅极形成具有沟槽壁并形成抗穿孔植入物的源体接触沟槽。

35. 发明授权

US09806175B2 Power MOSFET device structure for high frequency applications 有权
公开(公告)号：US09806175B2
公开(公告)日：2017-10-31
申请号：US14629229
申请日：2015-02-23
申请人： Anup Bhalla , Daniel Ng. , Tiesheng Li , Sik K. Lui
发明人： Anup Bhalla , Daniel Ng. , Tiesheng Li , Sik K. Lui
IPC分类号： H01L21/337 , H01L29/66 , H01L29/423 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

36. 发明授权

US08525260B2 Super junction device with deep trench and implant 有权
标题翻译：具有深沟槽和植入物的超连接装置
公开(公告)号：US08525260B2
公开(公告)日：2013-09-03
申请号：US12728044
申请日：2010-03-19
申请人： Tiesheng Li , Michael R. Hsing , Deming Xiao
发明人： Tiesheng Li , Michael R. Hsing , Deming Xiao
IPC分类号： H01L21/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/407 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： RESURF effect devices with both relatively deep trenches and relatively deep implants are described herein. Also, methods of fabricating such devices are described herein. A RESURF effect device may include alternating regions of first and second conductivity types where each of the second regions includes an implant region formed into a trench region of the second region.
摘要翻译：这里描述了具有相对较深的沟槽和相对深的植入物的RESURF效应装置。此外，这里描述了制造这种装置的方法。 RESURF效应器件可以包括第一和第二导电类型的交替区域，其中每个第二区域包括形成在第二区域的沟槽区域中的注入区域。

37. 发明授权

US08169801B2 Voltage converters with integrated low power leaker device and associated methods 有权
标题翻译：具有集成低功耗漏电装置和相关方法的电压转换器
公开(公告)号：US08169801B2
公开(公告)日：2012-05-01
申请号：US12474037
申请日：2009-05-28
申请人： Michael R. Hsing , Ognjen Milic , Tiesheng Li
发明人： Michael R. Hsing , Ognjen Milic , Tiesheng Li
IPC分类号： H02M3/335
CPC分类号： H02M1/36 , H01L27/085 , H01L27/0883 , H01L29/7803 , H01L29/7828 , H01L29/8083 , H02M3/33523 , H02M2001/0006
摘要： Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate.
摘要翻译：具有集成的低功率漏电装置和相关方法的电压转换器在本文中公开。在一个实施例中，电压转换器包括被配置为将第一电信号转换成不同于第一电信号的第二电信号的开关。电压转换器还包括可操作地耦合到开关的控制器和电耦合到控制器的漏电装置。控制器被配置为控制开关的导通和关闭门，并且漏电装置被配置为向控制器输送电力。漏电装置和开关形成在第一半导体衬底上，并且控制器形成在与第一半导体衬底分离的第二半导体衬底上。

38. 发明授权

US08008151B2 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US08008151B2
公开(公告)日：2011-08-30
申请号：US11983769
申请日：2007-11-09
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.
摘要翻译：一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

39. 发明申请

US20110198588A1 Polysilicon control etch-back indicator 有权
标题翻译：多晶硅控制回蚀指示器
公开(公告)号：US20110198588A1
公开(公告)日：2011-08-18
申请号：US13066583
申请日：2011-04-18
申请人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
发明人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L22/12 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
摘要翻译：本发明公开了一种用于在其上制造电子电路的半导体晶片。半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部具有较小的平面沟槽尺寸。

40. 发明授权

US07767526B1 High density trench MOSFET with single mask pre-defined gate and contact trenches 有权
标题翻译：具有单掩模预定义栅极和接触沟槽的高密度沟槽MOSFET
公开(公告)号：US07767526B1
公开(公告)日：2010-08-03
申请号：US12362414
申请日：2009-01-29
申请人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
发明人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/4236 , H01L29/78
摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
摘要翻译：沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。在半导体基板的表面上形成硬掩模。在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。接下来将栅极沟槽掩模施加在硬掩模的顶部上。栅极沟槽掩模覆盖主体接触沟槽，并且在栅极沟槽处具有比那些沟槽更宽的开口。栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。第一种导电材料可以填充栅沟以形成栅极。第二种导电材料可以填充身体接触沟槽以形成身体接触。

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