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31. 发明申请

US20100102400A1 LOW-K ISOLATION SPACERS FOR CONDUCTIVE REGIONS 有权
标题翻译：导电区域的低K隔离间隔
公开(公告)号：US20100102400A1
公开(公告)日：2010-04-29
申请号：US12650995
申请日：2009-12-31
申请人： Bernhard Sell
发明人： Bernhard Sell
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , Y10S257/90
摘要： A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall of a gate electrode in a MOS-FET device.
摘要翻译：描述了用于半导体结构中的导电区域的多组分低k隔离间隔物。在一个实施例中，替代隔离隔离器工艺被用于在MOS-FET器件中形成邻近栅电极的侧壁的双组分低k隔离隔离层。

32. 发明授权

US07687364B2 Low-k isolation spacers for conductive regions 失效
标题翻译：用于导电区域的低k隔离间隔物
公开(公告)号：US07687364B2
公开(公告)日：2010-03-30
申请号：US11500628
申请日：2006-08-07
申请人： Bernhard Sell
发明人： Bernhard Sell
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , Y10S257/90
摘要： A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall of a gate electrode in a MOS-FET device.
摘要翻译：描述了用于半导体结构中的导电区域的多组分低k隔离间隔物。在一个实施例中，替代隔离隔离器工艺被用于在MOS-FET器件中形成邻近栅电极的侧壁的双组分低k隔离隔离层。

33. 发明申请

US20090035911A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING ABRUPT ULTRA SHALLOW EPI-TIP REGIONS 审中-公开
标题翻译：形成具有超声波超低温区域的半导体器件的方法
公开(公告)号：US20090035911A1
公开(公告)日：2009-02-05
申请号：US11830155
申请日：2007-07-30
申请人： Willy Rachmady , Steven Keating , Bernhard Sell
发明人： Willy Rachmady , Steven Keating , Bernhard Sell
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor device having abrupt ultra shallow epi-tip regions comprises forming a gate stack on a crystalline substrate, performing a first ion implantation process to amorphisize a first pair of regions of the substrate disposed adjacent to and on laterally opposite sides of the gate stack, forming a pair of spacers on the substrate disposed on laterally opposite sides of the gate stack, performing a second ion implantation process to amorphisize a second pair of regions of the substrate that are disposed on laterally opposite sides of the gate stack and adjacent to the spacers, applying a selective wet etch chemistry to remove the amorphisized first and second pair of regions and form a pair of cavities on laterally opposite sides of the gate stack, and depositing a silicon alloy in the pair of cavities to form source and drain regions and source and drain epi-tip regions.
摘要翻译：一种用于形成具有突变的超浅表面尖端区域的半导体器件的方法包括在晶体衬底上形成栅极堆叠，执行第一离子注入工艺以使位于邻近和相对侧两侧的衬底的第一对区域非晶化所述栅堆叠在所述衬底上形成一对间隔物，所述衬底设置在所述栅堆叠的横向相对侧上，执行第二离子注入工艺以使位于所述栅叠层的横向相对侧上的所述衬底的第二对区域非晶化;以及邻近所述间隔物，施加选择性湿法蚀刻化学物质以去除所述非晶化的第一和第二对区域并在所述栅极堆叠的横向相对侧上形成一对空腔，以及在所述一对空腔中沉积硅合金以形成源和漏极区域和源极和漏极表面尖端区域。

34. 发明授权

US07335959B2 Device with stepped source/drain region profile 有权
标题翻译：具有阶梯式源极/漏极区域剖面的器件
公开(公告)号：US07335959B2
公开(公告)日：2008-02-26
申请号：US11031843
申请日：2005-01-06
申请人： Giuseppe Curello , Bernhard Sell , Sunit Tyagi , Chris Auth
发明人： Giuseppe Curello , Bernhard Sell , Sunit Tyagi , Chris Auth
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7842
摘要： Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.
摘要翻译：本发明的实施例提供了具有阶梯式源极和漏极区域的晶体管。台阶区域可以在通道区域中提供显着的应变，同时最小化电流泄漏。可以通过在基板中形成两个凹槽来形成阶梯状区域，以形成阶梯状凹陷，并且在凹部中形成源极/漏极区域。

35. 发明授权

US06835417B2 Method and device for depositing thin layers via ALD/CVD processes in combination with rapid thermal processes 有权
标题翻译：用于通过ALD / CVD工艺与快速热处理结合沉积薄层的方法和装置
公开(公告)号：US06835417B2
公开(公告)日：2004-12-28
申请号：US10375529
申请日：2003-02-27
申请人： Annette Saenger , Bernhard Sell , Harald Seidl , Thomas Hecht , Martin Gutsche
发明人： Annette Saenger , Bernhard Sell , Harald Seidl , Thomas Hecht , Martin Gutsche
IPC分类号： C23C1600
CPC分类号： C23C16/45527 , C23C16/34 , C23C16/40 , C23C16/42 , C23C16/45544 , C23C16/46 , C23C16/481
摘要： The ALD process chamber has heating radiation sources and the process sequence includes rapid temperature changes on a substrate surface of a substrate arranged in the ALD process chamber. The temperature changes are controlled and the ALD and CVD processes are optimized by in situ temperature steps, for example in order to produce nanolaminates.
摘要翻译： ALD处理室具有加热辐射源，并且工艺顺序包括在布置在ALD处理室中的衬底的衬底表面上的快速温度变化。控制温度变化，并通过原位温度步骤优化ALD和CVD工艺，例如为了生产纳米级氨基酸。

36. 发明授权

US06806037B2 Method for producing and/or renewing an etching mask 失效
标题翻译：用于制造和/或更新蚀刻掩模的方法
公开(公告)号：US06806037B2
公开(公告)日：2004-10-19
申请号：US10167785
申请日：2002-06-12
申请人： Matthias Goldbach , Thomas Hecht , Bernhard Sell
发明人： Matthias Goldbach , Thomas Hecht , Bernhard Sell
IPC分类号： G03F726
CPC分类号： H01L21/3086 , H01L21/3081 , H01L21/3085
摘要： An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.
摘要翻译：制造用于通过曝光的光致抗蚀剂层蚀刻基板的蚀刻掩模，使得暴露一次的区域尚未完全曝光，并且基于位于光致抗蚀剂层下方的反射层，额外暴露的区域完全暴露。因此，用于蚀刻衬底的第一蚀刻掩模可以通过第二蚀刻掩模来更新，因为施加到第一蚀刻掩模或代替第一蚀刻掩模的光致抗蚀剂层被暴露，使得已经被曝光一次还未完全曝光，并且基于位于光致抗蚀剂层下方并对应于第一蚀刻掩模的反射层另外暴露的区域被完全暴露。

37. 发明授权

US06674113B2 Trench capacitor and method for manufacturing the same 有权
标题翻译：沟槽电容器及其制造方法
公开(公告)号：US06674113B2
公开(公告)日：2004-01-06
申请号：US10254692
申请日：2002-09-25
申请人： Matthias Goldbach , Thomas Hecht , Jörn Lützen , Bernhard Sell
发明人： Matthias Goldbach , Thomas Hecht , Jörn Lützen , Bernhard Sell
IPC分类号： H01L2708
CPC分类号： H01L27/10861
摘要： A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.
摘要翻译：沟槽电容器具有布置在电容器电极之间的第一电容器电极，第二电容器电极和电介质。第一电容器电极具有延伸到基板中的管状结构。第二电容器电极包括与管状结构的内侧相对的第一部分，其间布置有电介质，第二部分与管状结构的外侧相反，电介质布置之间。

38. 发明授权

US07768074B2 Dual salicide integration for salicide through trench contacts and structures formed thereby 有权
标题翻译：通过沟槽接触和由此形成的结构，通过双层自对准硅化物一体化
公开(公告)号：US07768074B2
公开(公告)日：2010-08-03
申请号：US12319209
申请日：2008-12-31
申请人： Oleg Golonzka , Bernhard Sell
发明人： Oleg Golonzka , Bernhard Sell
IPC分类号： H01L23/62
CPC分类号： H01L21/823418 , H01L21/28123 , H01L21/823437 , H01L23/485 , H01L23/5226 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming an NMOS silicide on an NMOS source/drain contact area, forming a first contact metal on the NMOS silicide, polishing the first contact metal to expose a top surface of a PMOS source/drain region, and forming a PMOS silicide on the PMOS source/drain region.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在NMOS源极/漏极接触区域上形成NMOS硅化物，在NMOS硅化物上形成第一接触金属，抛光第一接触金属以暴露PMOS源极/漏极区的顶表面，以及形成PMOS硅化物在PMOS源极/漏极区域上。

39. 发明申请

US20100164002A1 DUAL SALICIDE INTEGRATION FOR SALICIDE THROUGH TRENCH CONTACTS AND STRUCTURES FORMED THEREBY 有权
标题翻译：通过TRENCH联系人和结构形成的杀真菌剂双重盐酸盐一体化
公开(公告)号：US20100164002A1
公开(公告)日：2010-07-01
申请号：US12319209
申请日：2008-12-31
申请人： Oleg Golonzka , Bernhard Sell
发明人： Oleg Golonzka , Bernhard Sell
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823418 , H01L21/28123 , H01L21/823437 , H01L23/485 , H01L23/5226 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming an NMOS silicide on an NMOS source/drain contact area, forming a first contact metal on the NMOS silicide, polishing the first contact metal to expose a top surface of a PMOS source/drain region, and forming a PMOS silicide on the PMOS source/drain region.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在NMOS源极/漏极接触区域上形成NMOS硅化物，在NMOS硅化物上形成第一接触金属，抛光第一接触金属以暴露PMOS源极/漏极区的顶表面，以及形成PMOS硅化物在PMOS源极/漏极区域上。

40. 发明授权

US07663192B2 CMOS device and method of manufacturing same 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US07663192B2
公开(公告)日：2010-02-16
申请号：US12215989
申请日：2008-06-30
申请人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel Aubertine
发明人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel Aubertine
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823835 , H01L29/66628 , H01L29/7834
摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.
摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134）绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

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