专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20070019348A1 Buffer circuit with enhanced overvoltage protection 有权
标题翻译：具有增强型过压保护功能的缓冲电路
公开(公告)号：US20070019348A1
公开(公告)日：2007-01-25
申请号：US11169139
申请日：2005-06-28
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
IPC分类号： H02H9/04
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.
摘要翻译：具有增强的过电压保护的缓冲电路包括可耦合到具有第一电压电平的第一电压源的核心缓冲电路。核心缓冲器电路被配置为接收第一信号并产生作为第一信号的函数的第二信号。缓冲电路还包括耦合在核心缓冲器电路和信号焊盘之间的保护电路。保护电路是可操作的：（i）当在信号焊盘处接收的第三信号超过第一电压电平达到第一量值时，将第一信号钳位到约第一电压电平; 和（ii）当第三信号小于或基本上等于第一电压电平时，产生基本上等于第三信号的第一信号。

32. 发明申请

US20060001449A1 Voltage level translator circuit 有权
公开(公告)号：US20060001449A1
公开(公告)日：2006-01-05
申请号：US10881192
申请日：2004-06-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Antonio Marques , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Antonio Marques , Bernard Morris
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logical state of the input signal. The latch circuit includes at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp is operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented thereto. The voltage level translator circuit includes a reference generator circuit for generating the control signal, a steady state value of the control signal being substantially equal to the first voltage level. The reference generator circuit is configured to adjust a voltage level of the control signal in response to the input signal.

33. 发明授权

US08159262B1 Impedance compensation in a buffer circuit 有权
标题翻译：缓冲电路中的阻抗补偿
公开(公告)号：US08159262B1
公开(公告)日：2012-04-17
申请号：US13030278
申请日：2011-02-18
申请人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman
发明人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman
IPC分类号： H03K17/16
CPC分类号： H03K19/00384
摘要： A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit having a pull-up portion comprising at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage in the buffer circuit and is operative to generate a first control signal indicating a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage over variations in PVT conditions to which the buffer circuit may be subjected. The compensation circuit further includes a control circuit generating first and second sets of digital control bits for compensating the pull-up and pull-down portions in the output stage over prescribed variations in PVT conditions. The second set of digital control bits is generated based at least on the first set of digital control bits and the first control signal.
摘要翻译：用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括具有包括至少一个PMOS晶体管的上拉部分和包括至少一个NMOS晶体管的下拉部分的监控电路。监视器电路被配置为跟踪缓冲器电路中的输出级的操作，并且可操作以产生第一控制信号，该第一控制信号指示输出级中的相应上拉和下拉部分的至少一个特征的状态，在缓冲电路可能遭受的PVT条件下。补偿电路还包括一个控制电路，产生第一和第二组数字控制位，用于通过PVT条件中规定的变化来补偿输出级中的上拉和下拉部分。至少基于第一组数字控制位和第一控制信号产生第二组数字控制位。

34. 发明申请

US20100141334A1 Bias circuit scheme for improved reliability in high voltage supply with low voltage device 有权
标题翻译：偏压电路方案，用于提高低压电源的可靠性
公开(公告)号：US20100141334A1
公开(公告)日：2010-06-10
申请号：US12330828
申请日：2008-12-09
申请人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
发明人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
IPC分类号： G05F1/10
CPC分类号： G05F3/16
摘要： Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.
摘要翻译：公开了一种偏置电路，其中第一电阻器连接在电源电压和反馈节点之间。电阻器连接在反馈节点和参考电源电压之间。电阻之间的连接限定了至少一个偏置电压。第二电阻器连接在反馈节点和第一漏极节点之间。第一场效应晶体管具有第一栅极节点，第一漏极节点和第一源节点。门节点连接到第一电源电压。第二场效应晶体管具有第二栅极节点，第二漏极节点和第二源节点。第二排水节点连接到第一源节点。第二栅极节点连接到偏置电压。第二源节点连接到输出信号节点。输出信号节点能够经历过冲电压。

35. 发明申请

US20070115030A1 Differential buffer circuit with reduced output common mode variation 失效
标题翻译：差分缓冲电路具有降低的输出共模变化
公开(公告)号：US20070115030A1
公开(公告)日：2007-05-24
申请号：US11285800
申请日：2005-11-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
IPC分类号： H03K19/094
CPC分类号： H04L25/0276
摘要： A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.
摘要翻译：差分缓冲电路包括电流源，电流吸收器和连接到第一节点处的电流源并在第二节点处连接到电流宿的开关电路。开关电路可操作以响应于至少第一控制信号选择性地控制流过缓冲电路的差分输出的电流的方向。缓冲电路还包括共模检测电路和共模控制电路。共模检测电路用于检测缓冲电路的输出共模电压，并产生表示输出共模电压的第二控制信号。共模控制电路包括连接到电流源的第一端子和连接到电流阱的第二端子。共模控制电路用于根据第二控制信号有选择地控制缓冲电路的输出共模电压。

36. 发明授权

US07218169B2 Reference compensation circuit 有权
标题翻译：参考补偿电路
公开(公告)号：US07218169B2
公开(公告)日：2007-05-15
申请号：US10744801
申请日：2003-12-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Christopher Kriz , Bernard Lee Morris , Jeffrey Jay Nagy , Stefan Allen Siegel
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Christopher Kriz , Bernard Lee Morris , Jeffrey Jay Nagy , Stefan Allen Siegel
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/245 , G05F3/247
摘要： A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.
摘要翻译：补偿电路包括参考电路，该参考电路包括参考NMOS器件和参考PMOS器件。参考电路可操作以产生第一参考信号和第二参考信号，第一参考信号是参考NMOS器件的处理特性，电压特性和温度特性中的至少一个的函数，第二参考信号信号是参考PMOS器件的工艺特性，电压特性和温度特性中的至少一个的函数。补偿电路还包括连接到参考电路的控制电路。控制电路可操作以接收第一和第二参考信号并产生一个或多个输出信号，用于补偿至少一个NMOS器件的工艺特性，电压特性和温度特性中的至少一个的变化，并且在响应于第一和第二参考信号，要补偿的电路中的至少一个PMOS器件可连接到控制电路。

37. 发明申请

US20060192587A1 Self-bypassing voltage level translator circuit 有权
公开(公告)号：US20060192587A1
公开(公告)日：2006-08-31
申请号：US11065785
申请日：2005-02-25
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K3/012 , H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.

38. 发明申请

US20060170461A1 Comparator circuit having reduced pulse width distortion 失效
标题翻译：比较器电路具有减小的脉冲宽度失真
公开(公告)号：US20060170461A1
公开(公告)日：2006-08-03
申请号：US11046995
申请日：2005-01-31
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
IPC分类号： H03K5/22
CPC分类号： H03K5/2481 , H03K5/12
摘要： A comparator circuit having reduced pulse width distortion includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. An output stage is included in the comparator circuit for receiving the difference signal and for generating an output signal of the comparator circuit, the output signal being representative of the difference signal, the output stage having a switching point associated therewith. The comparator circuit further includes a voltage source coupled to the output of the differential amplifier. The voltage source is operative to generate a reference signal for establishing a common-mode voltage of the difference signal generated by the differential amplifier. The reference signal is substantially centered about the switching point of the output stage and substantially tracks the switching point over variations in process, voltage and/or temperature conditions to which the comparator circuit is subjected.
摘要翻译：具有减小的脉冲宽度失真的比较器电路包括差分放大器，其操作以接收至少第一和第二信号并且放大第一和第二信号之间的差。差分放大器在其输出处产生差分信号，其作为第一和第二信号之间的差异的函数。输出级包括在比较器电路中，用于接收差分信号并产生比较器电路的输出信号，该输出信号代表差分信号，输出级具有与之相关的切换点。比较器电路还包括耦合到差分放大器的输出的电压源。电压源用于产生用于建立由差分放大器产生的差分信号的共模电压的参考信号。参考信号基本上以输出级的切换点为中心，并且基本上跟踪比较器电路所经受的过程，电压和/或温度条件变化的切换点。

39. 发明授权

US07936209B2 I/O buffer with low voltage semiconductor devices 失效
标题翻译：具有低电压半导体器件的I / O缓冲器
公开(公告)号：US07936209B2
公开(公告)日：2011-05-03
申请号：US12428556
申请日：2009-04-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K17/0822 , H03K19/018528
摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.
摘要翻译：所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。从缓冲器的工作电压产生第一和第二偏置电压。从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压缓冲。第三和第四偏置电压分别提供给第一和第二过压保护电路。

40. 发明申请

US20070176635A1 Voltage level translator circuit with wide supply voltage range 有权
标题翻译：具有宽电源电压范围的电压电平转换电路
公开(公告)号：US20070176635A1
公开(公告)日：2007-08-02
申请号：US11342175
申请日：2006-01-27
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , H03K3/356104
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.
摘要翻译：用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，该输入级包括至少一个具有第一阈值电压相关联。电压电平转换器电路还包括锁存电路，其操作以存储表示输入信号的逻辑状态的信号，所述锁存电路包括具有与其相关联的第二阈值电压的至少一个晶体管器件，所述第二阈值电压大于第一阈值电压。电压钳位电路连接在输入级和锁存电路之间。电压钳位电路用于限制输入级两端的电压，输入级两端的电压幅度作为第一和第二电压源之间的电压差的函数被控制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式