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31. 发明授权

US06071817A Isolation method utilizing a high pressure oxidation 失效
标题翻译：采用高压氧化的隔离方法
公开(公告)号：US06071817A
公开(公告)日：2000-06-06
申请号：US046242
申请日：1998-03-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs
发明人： Derryl D. J. Allman , Kenneth P. Fuchs
IPC分类号： H01L21/316 , H01L21/762 , H01L21/00
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/76202 , H01L21/76205
摘要： The present invention applies a silicon nitride or the like as a mask over portions of a substrate, such as an active region, where oxide growth is undesired. Thereafter, without the formation of a recess in the substrate, a high pressure oxidation process is used to grow an oxide, preferably in a furnace. The oxide thus grows into the non-masked areas of the substrate, as well as over the silicon nitride used as a mask. Thereafter, a chemical-mechanical polish is used to etch away undesired oxide, with the silicon nitride being used as an endpoint to terminate the polish operation.
摘要翻译：本发明将氮化硅等作为掩模应用于诸如活性区域的基底的不希望有氧化物生长的部分上。此后，在衬底中不形成凹陷的情况下，使用高压氧化工艺来生长氧化物，优选在炉中生长氧化物。因此，氧化物生长到衬底的非掩蔽区域中，以及用作掩模的氮化硅上方。此后，使用化学机械抛光剂来蚀刻掉不期望的氧化物，其中氮化硅用作端点终止抛光操作。

32. 发明授权

US5728626A Spin-on conductor process for integrated circuits 失效
标题翻译：集成电路的旋转导体工艺
公开(公告)号：US5728626A
公开(公告)日：1998-03-17
申请号：US553788
申请日：1995-10-23
申请人： Derryl D. J. Allman , Steven S. Lee
发明人： Derryl D. J. Allman , Steven S. Lee
IPC分类号： H01L21/288 , H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L29/78 , B05D3/02 , B05D5/12 , H01L21/445
CPC分类号： H01L21/288 , H01L21/7684 , H01L21/76877
摘要： A method of planarizing a non-planar substrate, such as filling vias and contact holes, spreads a suspension of a conducting material suspended in a liquid on a substrate. The suspension includes an organometallic material, preferably with particles of a polymerized tin or indium alkoxide. The material is spread by spinning the substrate after applying the suspension. The carrier liquid and organic groups are removed by baking and curing at elevated temperatures, thereby depositing the conductive material on the substrate in a layer which is more planar than the substrate and which has regions of greater and lesser thickness. A relatively brief etch step removes conductive material from regions of lesser thickness, leaving material filling vias or contact holes.
摘要翻译：平面化非平面衬底（例如填充通孔和接触孔）的方法将悬浮在液体中的导电材料的悬浮液铺展在衬底上。悬浮液包括有机金属材料，优选具有聚合的锡或烷氧基铟的颗粒。施加悬浮液后，通过旋转基材来铺展材料。载体液体和有机基团通过在升高的温度下烘烤和固化来除去，从而将导电材料沉积在基底上比基底更平坦且具有较大和较小厚度的区域的层中。相对短暂的蚀刻步骤从较小厚度的区域去除导电材料，留下填充通孔或接触孔的材料。

33. 发明授权

US5665845A Electronic device with a spin-on glass dielectric layer 失效
标题翻译：具有旋涂玻璃介电层的电子器件
公开(公告)号：US5665845A
公开(公告)日：1997-09-09
申请号：US609589
申请日：1996-03-01
申请人： Derryl D. J. Allman
发明人： Derryl D. J. Allman
IPC分类号： G03F1/08 , G03F7/09 , H01L21/027 , H01L21/312 , H01L23/532 , C08G79/08
CPC分类号： H01L21/0276 , G03F7/091 , G03F7/094 , H01L21/02129 , H01L21/02216 , H01L21/02282 , H01L21/3122 , H01L23/5329 , H01L2924/0002 , Y10T428/31663
摘要： There is provided electronic devices with dielectric layers obtained from boron-oxide doped, spin-on glass formulations which form glassy layers with high oxygen resistance. Suitable electronic devices include integrated circuits. With high oxygen resistance, the glassy layer formed maintains its integrity in subsequent processing. Also provided is a method for preparing boron-oxide doped, spin-on glass formulations with a high carbon content having a silane adhesion promoter and boron-dopant incorporated therein.
摘要翻译：提供具有由氧化硼掺杂的旋涂玻璃配方获得的电介质层的电子器件，其形成具有高耐氧性的玻璃质层。合适的电子设备包括集成电路。具有高耐氧性，形成的玻璃状层在后续处理中保持其完整性。还提供了一种制备具有高碳含量的氧化硼掺杂的旋涂玻璃配方的方法，其具有硅烷粘附促进剂和掺入硼掺杂剂。

34. 发明授权

US5645736A Method for polishing a wafer 失效
标题翻译：抛光晶圆的方法
公开(公告)号：US5645736A
公开(公告)日：1997-07-08
申请号：US580674
申请日：1995-12-29
申请人： Derryl D. J. Allman
发明人： Derryl D. J. Allman
IPC分类号： H01L21/304 , B24B37/04 , C09G1/02 , H01L21/3105 , C09G1/00 , B24B1/00
CPC分类号： H01L21/31053 , B24B37/044 , C09G1/02
摘要： A method is shown for polishing a workpiece such as a semiconductor wafer. A polishing composition is first formed which includes (1) a polishing media particle; and (2) a film forming binder for suspending the particle and forming a temporary film on an exposed surface of the workpiece, the temporary film being dissolvable in a subsequently applied polishing wash, whereby the polishing media particle is freed to polish the workpiece. The polishing composition is applied to the surface of the semiconductor wafer in a spin coating operation and thereafter cured in a hot plate bake or a furnace operation. In order to polish the workpiece, a polishing wash is applied to either or both of the surface of the workpiece or a polishing pad and thereafter causing the pad to be sufficiently proximate to the surface of the workpiece at a pressure and for a time sufficient to polish and planarize the workpiece.
摘要翻译：示出了用于抛光诸如半导体晶片的工件的方法。首先形成抛光组合物，其包括（1）抛光介质颗粒; 和（2）用于使颗粒悬浮并在工件的暴露表面上形成临时膜的成膜粘合剂，临时膜可以在随后施加的抛光洗涤中溶解，由此抛光介质颗粒被释放以抛光工件。抛光组合物在旋转涂布操作中施加到半导体晶片的表面，然后在热板烘烤或炉操作中固化。为了抛光工件，抛光洗涤被施加到工件的表面或抛光垫的任何一个或两者上，然后在足够的压力下将焊盘充分靠近工件的表面，并且持续足够的时间抛光并平坦化工件。

35. 发明授权

US5527872A Electronic device with a spin-on glass dielectric layer 失效
标题翻译：具有旋涂玻璃介电层的电子器件
公开(公告)号：US5527872A
公开(公告)日：1996-06-18
申请号：US214477
申请日：1994-03-17
申请人： Derryl D. J. Allman
发明人： Derryl D. J. Allman
IPC分类号： G03F1/08 , G03F7/09 , H01L21/027 , H01L21/312 , H01L23/532 , C08G77/08
CPC分类号： H01L21/0276 , G03F7/091 , G03F7/094 , H01L21/02129 , H01L21/02216 , H01L21/02282 , H01L21/3122 , H01L23/5329 , H01L2924/0002 , Y10T428/31663
摘要： There is provided electronic devices with dielectric layers obtained from boron-oxide doped, spin-on glass formulations which form glassy layers with high oxygen resistance. Suitable electronic devices include integrated circuits. With high oxygen resistance, the glassy layer formed maintains its integrity in subsequent processing. Also provided is a method for preparing boron-oxide doped, spin-on glass formulations with a high carbon content having a silane adhesion promoter and boron-dopant incorporated therein.
摘要翻译：提供具有由氧化硼掺杂的旋涂玻璃配方获得的电介质层的电子器件，其形成具有高耐氧性的玻璃质层。合适的电子设备包括集成电路。具有高耐氧性，形成的玻璃状层在后续处理中保持其完整性。还提供了一种制备具有高碳含量的氧化硼掺杂的旋涂玻璃配方的方法，其具有硅烷粘附促进剂和掺入硼掺杂剂。

36. 发明授权

US5308790A Selective sidewall diffusion process using doped SOG 失效
标题翻译：使用掺杂SOG的选择性侧壁扩散过程
公开(公告)号：US5308790A
公开(公告)日：1994-05-03
申请号：US961967
申请日：1992-10-16
申请人： Derryl D. J. Allman , Gayle W. Miller
发明人： Derryl D. J. Allman , Gayle W. Miller
IPC分类号： H01L21/225 , H01L21/316 , H01L21/334 , H01L21/335
CPC分类号： H01L29/66181 , H01L21/2255 , H01L29/66416 , Y10S148/031
摘要： A selective sidewall diffusion process using doped SOG. A substrate is processed to form raised portions or pedestals, having sidewalls, and trenches. A first layer, either a doped SOG layer or undoped oxide layer, may be deposited onto the substrate adjacent the sidewalls. The first layer is densified. A second layer may be deposited on the first layer. The second layer is a doped SOG layer. The second layer is densified and the dopant is driven into the sidewalls to form shallow junctions.
摘要翻译：使用掺杂SOG的选择性侧壁扩散工艺。处理衬底以形成具有侧壁和沟槽的凸起部分或基座。掺杂的SOG层或未掺杂的氧化物层的第一层可以沉积在邻近侧壁的衬底上。第一层被致密化。第二层可以沉积在第一层上。第二层是掺杂的SOG层。第二层被致密化并且掺杂剂被驱动到侧壁中以形成浅结。

37. 发明授权

US07118985B2 Method of forming a metal-insulator-metal capacitor in an interconnect cavity 有权
标题翻译：在互连腔中形成金属 - 绝缘体 - 金属电容器的方法
公开(公告)号：US07118985B2
公开(公告)日：2006-10-10
申请号：US10260824
申请日：2002-09-27
申请人： Derryl D. J. Allman , Kenneth Fuchs
发明人： Derryl D. J. Allman , Kenneth Fuchs
IPC分类号： H01L21/768 , H01L21/8242
CPC分类号： H01L28/40 , H01L21/768 , H01L28/75
摘要： A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.
摘要翻译：金属 - 绝缘体 - 金属电容器嵌入在集成电路（IC）的互连层中。互连层具有空腔，并且电容器形成在空腔中，电容器的一个板与互连层的导电层成一体，因此电容器板与互连层电连通。互连层具有多个导电层，包括在制造IC期间在特定温度下经受变形的诸如铝的层，并且空腔延伸穿过该层。互连层的剩余导电层限定电容器板中的一个，并且在腔内形成介电层和另一电容器板。通过大致相同长度的互连电连接到顶板并且通过互连层连接到底板。

38. 发明授权

US07023067B2 Bond pad design 失效
标题翻译：焊盘设计
公开(公告)号：US07023067B2
公开(公告)日：2006-04-04
申请号：US10341082
申请日：2003-01-13
申请人： Derryl D. J. Allman , Charles E. May
发明人： Derryl D. J. Allman , Charles E. May
IPC分类号： H01L31/10
CPC分类号： H01L24/05 , H01L24/48 , H01L2224/04042 , H01L2224/05082 , H01L2224/05093 , H01L2224/05095 , H01L2224/05187 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/05647 , H01L2224/4807 , H01L2224/4845 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2224/45099 , H01L2924/00
摘要： A bonding pad for an integrated circuit, where the bonding pad overlies a fragile dielectric layer. A lower metal layer stack overlies the fragile dielectric layer, and a hard dielectric layer overlies the lower metal layer stack. An upper metal layer stack overlies the hard dielectric layer, where the upper metal layer stack forms voids extending into the upper metal layer stack from an exposed upper surface of the upper metal layer stack. The voids define deformable protrusions in the upper surface of the upper metal layer stack, for at least partially absorbing forces applied to the bonding pad during a bonding operation. Electrically conductive vias extend from the lower metal layer stack through the hard dielectric layer to the upper metal layer stack, and electrically connect the lower metal layer stack to the upper metal layer stack.
摘要翻译：一种用于集成电路的焊盘，其中所述焊盘覆盖在脆性介电层上。下部金属层堆叠在脆性介电层之上，并且硬介电层覆盖在下部金属层堆叠上。上部金属层堆叠在硬介电层之上，其中上部金属层堆叠形成从上部金属层堆叠的暴露的上表面延伸到上部金属层堆叠中的空隙。空隙限定上金属层堆叠的上表面中的可变形突起，用于在粘合操作期间至少部分地吸收施加到接合焊盘的力。导电通孔从下金属层堆叠穿过硬介电层延伸到上金属层堆叠，并将下金属层堆叠电连接到上金属层堆叠。

39. 发明授权

US06576544B1 Local interconnect 有权
标题翻译：本地互连
公开(公告)号：US06576544B1
公开(公告)日：2003-06-10
申请号：US09966464
申请日：2001-09-28
申请人： Derryl D. J. Allman , James R. Hightower , Phonesavanh Saopraseuth
发明人： Derryl D. J. Allman , James R. Hightower , Phonesavanh Saopraseuth
IPC分类号： H01L214763
CPC分类号： H01L21/76895
摘要： A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels. Furthermore, by allowing these local electrical interconnections to be produced during the same manufacturing step as the macro elements of the integrated circuit, the method of the present invention tends to reduce the number of steps required to produce an integrated circuit.
摘要翻译：本发明提供一种用于形成集成电路的电互连电平和电路元件的方法。该方法利用比通常用于形成诸如氮化钛的电互连的金属具有更高电阻的相对薄的导电材料层，以在集成电路的电路元件之间提供相对较短的局部互连。此外，这种相同的薄导电材料用于在集成电路中形成诸如电容器，电阻器和熔丝的宏观元件。通过允许从互连级别去除耗费空间的横向电互连线，本发明增加了电互连级别的布线密度。此外，通过在与集成电路的宏观元件相同的制造步骤中产生这些局部电互连，本发明的方法倾向于减少制造集成电路所需的步骤数量。

40. 发明授权

US06570221B1 Bonding of silicon wafers 失效
标题翻译：硅晶片的接合
公开(公告)号：US06570221B1
公开(公告)日：2003-05-27
申请号：US08097183
申请日：1993-07-27
申请人： Derryl D. J. Allman
发明人： Derryl D. J. Allman
IPC分类号： H01L2701
CPC分类号： H01L21/8221 , H01L27/0688 , Y10S438/974
摘要： The invention concerns the use of spin-on-glass (SOG) to bond two layers of semiconductor together, in order to form a Silicon-on-Insulator (SOI) structure. One type of SOG is a cross-linked siloxane polymer, preferably of the poly-organo-siloxane type, comprising a carbon content of at least 5 atomic weight percent.
摘要翻译：本发明涉及使用旋涂玻璃（SOG）将两层半导体结合在一起，以便形成绝缘体上硅（SOI）结构。一种SOG是交联硅氧烷聚合物，优选为聚有机硅氧烷型，其含有至少5原子％的碳含量。

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