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31. 发明授权

US08338258B2 Embedded stressor for semiconductor structures 有权
标题翻译：半导体结构的嵌入式应力器
公开(公告)号：US08338258B2
公开(公告)日：2012-12-25
申请号：US12625827
申请日：2009-11-25
申请人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
发明人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/66651 , H01L29/66772 , H01L29/78687
摘要： A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.
摘要翻译：一种在半导体结构内制造嵌入式应力器的方法以及包括所述嵌入式应力器的半导体结构的方法包括在所述应力源材料的衬底上形成形成虚拟栅极叠层的方法，将所述衬底的与所述虚拟栅极堆叠相邻的衬底的侧壁部分，应力器具有成角度的侧壁部分，将导电材料形成在嵌入式应力源的成角度的侧壁部分上，去除虚拟栅极堆叠，平坦化导电材料，以及在导电材料上形成栅极叠层。

32. 发明授权

US08338256B2 Multi-gate transistor having sidewall contacts 有权
标题翻译：具有侧壁接触的多栅极晶体管
公开(公告)号：US08338256B2
公开(公告)日：2012-12-25
申请号：US12832829
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译：一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

33. 发明申请

US20120299118A1 Multiple Threshold Voltages in Field Effect Transistor Devices 失效
标题翻译：场效应晶体管器件中的多个阈值电压
公开(公告)号：US20120299118A1
公开(公告)日：2012-11-29
申请号：US13560240
申请日：2012-07-27
申请人： Dechao Guo , Keith Kwong Hon Wong
发明人： Dechao Guo , Keith Kwong Hon Wong
IPC分类号： H01L27/088
CPC分类号： H01L29/78696 , H01L21/845 , H01L27/1211 , H01L29/42392 , H01L29/66795
摘要： A field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, and an ion doped drain region connected to the first conductive channel and the second conductive channel.
摘要翻译：场效应晶体管器件包括设置在衬底上的第一导电沟道，设置在衬底上的第二导电沟道，形成在第一导电沟道上的第一栅极叠层，第一栅叠层包括具有第一氧含量的金属层，形成在第二导电沟道上的第二栅极堆叠a，第二栅极堆叠包括具有第二氧的金属层，连接到第一导电沟道和第二导电沟道的离子掺杂源区，以及连接到第二导电沟的离子掺杂漏极区第一导电沟道和第二导电沟道。

34. 发明申请

US20120261728A1 EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES 有权
标题翻译：用于半导体结构的嵌入式压电器
公开(公告)号：US20120261728A1
公开(公告)日：2012-10-18
申请号：US13529558
申请日：2012-06-21
申请人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
发明人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/66651 , H01L29/66772 , H01L29/78687
摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 设置在所述栅极堆叠的横向相对侧上的多个间隔件; 邻近间隔物的源极和漏极区域以及位于栅极堆叠下方并设置在源极和漏极区域之间的沟道区域; 以及位于所述沟道区域的下方并嵌入在所述半导体衬底内的应力器，所述嵌入式应力器由三角形形成。

35. 发明申请

US20120187505A1 Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation 审中-公开
标题翻译：自对准III-V MOSFET制造，具有原位III-V外延和原位金属外延和接触形成
公开(公告)号：US20120187505A1
公开(公告)日：2012-07-26
申请号：US13013206
申请日：2011-01-25
申请人： Dechao Guo , Shu-Jen Han , Jeehwan Kim , Kuen-Ting Shiu
发明人： Dechao Guo , Shu-Jen Han , Jeehwan Kim , Kuen-Ting Shiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/8252 , H01L21/26546 , H01L21/28575 , H01L21/3245 , H01L29/0847 , H01L29/201 , H01L29/207 , H01L29/41783 , H01L29/452 , H01L29/66446 , H01L29/66477 , H01L29/66522 , H01L29/66628 , H01L29/78
摘要： A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.
摘要翻译：一种用于形成晶体管的方法，包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物与源/漏区相邻形成的区域。该方法包括在源极/漏极区域上生长凸起的源极/漏极区域，生长的升高的源极/漏极区域包括III-V半导体材料，以及在生长的升高的源极/漏极区域上生长的金属接触。形成晶体管的另一种方法包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物与源/漏区相邻形成的区域。该方法包括在源/漏区上生长金属接触。还公开了晶体管和计算机程序产品。

36. 发明申请

US20120112310A1 DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE 有权
标题翻译：用于半导体结构的扩散面板
公开(公告)号：US20120112310A1
公开(公告)日：2012-05-10
申请号：US13351041
申请日：2012-01-16
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L29/06
CPC分类号： H01L21/76224 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.
摘要翻译：在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

37. 发明申请

US20110315961A1 Ultrathin Spacer Formation for Carbon-Based FET 有权
标题翻译：碳基FET的超薄间隔物形成
公开(公告)号：US20110315961A1
公开(公告)日：2011-12-29
申请号：US12826221
申请日：2010-06-29
申请人： Zhihong Chen , Dechao Guo , Shu-Jen Han , Kai Zhao
发明人： Zhihong Chen , Dechao Guo , Shu-Jen Han , Kai Zhao
IPC分类号： H01L29/76 , H01L29/78 , H01L21/334
CPC分类号： H01L29/1606 , H01L29/4908 , H01L29/66742 , H01L29/7781 , H01L29/78684
摘要： A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.
摘要翻译：一种用于形成碳基场效应晶体管（FET）的方法包括：在位于衬底上的碳层上沉积第一介电层; 在所述第一电介质层上形成栅电极; 蚀刻第一介电层的暴露部分以暴露碳层的一部分; 在所述栅电极上沉积第二电介质层以形成间隔物，其中所述第二电介质层通过原子层沉积（ALD）沉积，并且其中所述第二电介质层不在所述碳层的暴露部分上形成; 在碳层上形成源极和漏极接触，并在栅电极上形成栅极接触以形成碳基FET。

38. 发明申请

US20110248321A1 Self-Aligned Contacts for Field Effect Transistor Devices 有权
标题翻译：场效应晶体管器件的自对准触点
公开(公告)号：US20110248321A1
公开(公告)日：2011-10-13
申请号：US12757201
申请日：2010-04-09
申请人： Dechao Guo , Wilfried E. Haensch , Xinhui Wang , Keith Kwong Hon Wong
发明人： Dechao Guo , Wilfried E. Haensch , Xinhui Wang , Keith Kwong Hon Wong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/28114 , H01L21/28525 , H01L21/76897 , H01L21/78 , H01L29/66545
摘要： A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.
摘要翻译：一种用于形成场效应晶体管的方法，包括：形成栅极叠层，与栅叠层的相对侧相邻的间隔物，在间隔物的相对侧上的硅化物源区和硅化物漏极区，在源区上外延生长硅，漏区; 在栅极堆叠和间隔物上形成衬垫层，去除衬里层的一部分以露出硬掩模层的一部分，去除硬掩模层的暴露部分以暴露栅堆叠的硅层，将暴露的硅去除暴露栅叠层，源极区和漏区的金属层的一部分; 以及在栅叠层，硅化物源区和硅化物漏极区的金属层上沉积导电材料。

39. 发明申请

US20110241120A1 Field Effect Transistor Device and Fabrication 有权
标题翻译：场效应晶体管器件和制造
公开(公告)号：US20110241120A1
公开(公告)日：2011-10-06
申请号：US12754917
申请日：2010-04-06
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/42368 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L29/66477
摘要： A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.
摘要翻译：一种用于形成场效应晶体管（FET）器件的方法，包括在衬底上形成电介质层，在电介质层上形成第一金属层，去除第一金属层的一部分以露出电介质层的一部分，形成在所述电介质层和所述第一金属层上的第二金属层，以及去除所述第一金属层和所述第二金属层的一部分，以限定第一FET器件和第二FET器件之间的边界区域。

40. 发明申请

US20110115044A1 DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE 有权
标题翻译：用于半导体结构的扩散面板
公开(公告)号：US20110115044A1
公开(公告)日：2011-05-19
申请号：US12621216
申请日：2009-11-18
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.
摘要翻译：在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

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