专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20110320695A1 MITIGATING BUSY TIME IN A HIGH PERFORMANCE CACHE 失效
标题翻译：在高性能缓存中缓解繁忙时间
公开(公告)号：US20110320695A1
公开(公告)日：2011-12-29
申请号：US12821736
申请日：2010-06-23
申请人： Deanna P. BERGER , Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diana L. Orf , Robert J. Sonnelitter, III
发明人： Deanna P. BERGER , Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diana L. Orf , Robert J. Sonnelitter, III
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0857 , G06F12/084 , G06F12/0846 , G06F12/0855 , G06F2212/1024 , G06F2212/281
摘要： Various embodiments of the present invention mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.
摘要翻译：本发明的各种实施例减轻了分级存储器存储器高速缓存结构中的繁忙时间。在一个实施例中，与存储器高速缓存相关联的高速缓存目录被分成多个部分，每个部分与部分存储器高速缓存相关联。支持高速缓存目录的多个部分之间的同时高速缓存查找操作和缓存写入操作。在通信地耦合到高速缓存目录的多个部分的共享高速缓存管道中同时处理两个或更多个存储命令。

32. 发明申请

US20110314211A1 RECOVER STORE DATA MERGING 失效
标题翻译：恢复存储数据合并
公开(公告)号：US20110314211A1
公开(公告)日：2011-12-22
申请号：US12820511
申请日：2010-06-22
申请人： Deanna P. BERGER , Michael F. Fee , Christine C. Jones , Diana L. Orf , Robert J. Sonnelitter, III
发明人： Deanna P. BERGER , Michael F. Fee , Christine C. Jones , Diana L. Orf , Robert J. Sonnelitter, III
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F11/1064 , G06F12/0802
摘要： Various embodiments of the present invention merge data in a cache memory. In one embodiment a set of store data is received from a processing core. A store merge command and a merge mask from are also received from the processing core. A portion of the store data to perform a merging operation thereon is identified based on the store merge command. A sub-portion of the portion of the store data to be merged with a corresponding set of data from a cache memory is identified based on the merge mask. The sub-portion is merged with the corresponding set of data from the cache memory.
摘要翻译：本发明的各种实施例将数据合并在高速缓冲存储器中。在一个实施例中，从处理核心接收一组存储数据。还从处理核心接收存储合并命令和合并掩码。基于存储合并命令来识别用于执行其上的合并操作的存储数据的一部分。基于合并掩码来识别与高速缓冲存储器的相应的数据集合合并的存储数据的一部分的子部分。子部分与来自高速缓冲存储器的相应的数据集合合并。

33. 发明授权

US08447930B2 Managing in-line store throughput reduction 失效
公开(公告)号：US08447930B2
公开(公告)日：2013-05-21
申请号：US12820528
申请日：2010-06-22
申请人： Deanna P. Berger , Michael F. Fee , Christine C. Jones , Diana L. Orf , Robert J. Sonnelitter, III
发明人： Deanna P. Berger , Michael F. Fee , Christine C. Jones , Diana L. Orf , Robert J. Sonnelitter, III
IPC分类号： G06F12/14
CPC分类号： G06F12/0811 , G06F9/524 , G06F12/0855 , G06F12/0897
摘要： Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.

34. 发明申请

US20090240891A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DATA BUFFERS PARTITIONED FROM A CACHE ARRAY 有权
标题翻译：方法，系统和计算机程序产品用于从缓存区域分配的数据缓冲区
公开(公告)号：US20090240891A1
公开(公告)日：2009-09-24
申请号：US12051244
申请日：2008-03-19
申请人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
发明人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F2212/2515
摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.
摘要翻译：从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态，响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

35. 发明授权

US08250305B2 Method, system and computer program product for data buffers partitioned from a cache array 有权
标题翻译：从缓存阵列分区的数据缓冲区的方法，系统和计算机程序产品
公开(公告)号：US08250305B2
公开(公告)日：2012-08-21
申请号：US12051244
申请日：2008-03-19
申请人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
发明人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/126 , G06F2212/2515
摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.
摘要翻译：从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态，响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

36. 发明申请

US20110314212A1 MANAGING IN-LINE STORE THROUGHPUT REDUCTION 失效
标题翻译：管理线上存储通过减少
公开(公告)号：US20110314212A1
公开(公告)日：2011-12-22
申请号：US12820528
申请日：2010-06-22
申请人： DEANNA P. BERGER , Michael F. Fee , Christine C. Jones , Diana L. Orf , Robert J. Sonnelitter, III
发明人： DEANNA P. BERGER , Michael F. Fee , Christine C. Jones , Diana L. Orf , Robert J. Sonnelitter, III
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0811 , G06F9/524 , G06F12/0855 , G06F12/0897
摘要： Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.
摘要翻译：本发明的各种实施例管理分层存储存储器高速缓存结构。存储请求队列与多个处理核心中的处理核心相关联。确定至少一个阻塞条件已经在存储请求队列中发生。响应于发生的阻塞状态，多个非存储请求和与多个处理核心中的剩余处理核心集相关联的一组存储请求被动态阻止访问存储器高速缓存。

37. 发明申请

US20110258394A1 MERGING DATA IN AN L2 CACHE MEMORY 有权
标题翻译：兼容L2缓存中的数据
公开(公告)号：US20110258394A1
公开(公告)日：2011-10-20
申请号：US13173840
申请日：2011-06-30
申请人： Deanna P. Dunn , Robert J. Sonnelitter, III , Gary E. Strait
发明人： Deanna P. Dunn , Robert J. Sonnelitter, III , Gary E. Strait
IPC分类号： G06F12/08
CPC分类号： G06F13/28 , G06F12/0866
摘要： A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining that the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data.
摘要翻译：一种用于合并数据的方法，包括接收来自输入/输出设备的请求以合并数据，其中所述数据的合并包括所述数据的操作，确定所述数据存在于与所述数据本地通信的本地高速缓冲存储器中输入/输出设备，如果数据不存在于本地高速缓冲存储器中，则从远程高速缓冲存储器或主存储器将数据提取到本地高速缓冲存储器，根据请求合并数据以获得合并数据，并存储合并的数据在本地高速缓存中，其中在不使用控制流中的存储器控制器或合并数据的数据流的情况下执行数据的合并。

38. 发明申请

US20090210661A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AN IMPLICIT PREDICTED RETURN FROM A PREDICTED SUBROUTINE 失效
标题翻译：方法，系统和计算机程序产品预测从预测的SUBROUTINE返回
公开(公告)号：US20090210661A1
公开(公告)日：2009-08-20
申请号：US12034066
申请日：2008-02-20
申请人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , Charles F. Webb
发明人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , Charles F. Webb
IPC分类号： G06F9/312
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/3806 , G06F9/3844
摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.
摘要翻译：提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

39. 发明授权

US08850129B2 Memory ordered store system in a multiprocessor computer system 有权
标题翻译：内存订购存储系统在多处理器计算机系统中
公开(公告)号：US08850129B2
公开(公告)日：2014-09-30
申请号：US12822331
申请日：2010-06-24
申请人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
发明人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
IPC分类号： G06F12/02 , G06F12/08 , G06F9/38 , G06F12/10 , G06F9/52
CPC分类号： G06F12/0815 , G06F9/3842 , G06F9/528 , G06F12/0828 , G06F12/0831 , G06F12/0862 , G06F12/1054 , G06F2212/1016 , G06F2212/507 , G06F2212/621
摘要： A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.
摘要翻译：提供了一种用于以快速的顺序将数据存储在计算机系统的存储器中的系统和计算机实现的方法。该方法包括向存储器启动第一个存储。启动等待计数器。当等待计数器到期时，第二家存储器被推测启动。当第二个存储在第一个存储到存储器之前实现相关性时，第二个存储器的存储被取消。

40. 发明授权

US07822954B2 Methods, systems, and computer program products for recovering from branch prediction latency 有权
标题翻译：从分支预测延迟中恢复的方法，系统和计算机程序产品
公开(公告)号：US07822954B2
公开(公告)日：2010-10-26
申请号：US12034112
申请日：2008-02-20
申请人： John W. Ward, III , Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
发明人： John W. Ward, III , Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/383 , G06F9/3802 , G06F9/3861
摘要： A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.
摘要翻译：分支预测算法用于生成是否采用分支的预测。取出一个或多个指令，使得对于每个获取的指令，预测启动在分支的预测目标处的指令的获取。执行测试以确定预测是否相对于获取的指令生成较晚，使得如果稍后检测到该分支被误预测，则该检测可以与后期预测相关。当预测相对于所获取的指令生成较晚时，通过利用由潜在预测发起的提取来选择潜在预测，使得新的获取不被开始。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式