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31. 发明授权

US06531373B2 Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements 有权
标题翻译：在硫族化物元素中使用绝缘体上硅绝缘体形成相变存储单元的方法
公开(公告)号：US06531373B2
公开(公告)日：2003-03-11
申请号：US09751485
申请日：2000-12-27
申请人： Manzur Gill , Tyler Lowrey
发明人： Manzur Gill , Tyler Lowrey
IPC分类号： H01L2176
CPC分类号： G11C13/0004 , G11C13/003 , G11C2213/74 , G11C2213/79 , H01L27/12 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683
摘要： The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure.
摘要翻译：本发明涉及在存储材料的硫族化物体积中使用SOI的相变存储器件。寄生电容（垂直和横向）在本发明的结构中被减少或消除。

32. 发明授权

US5420060A Method of making contract-free floating-gate memory array with silicided buried bitlines and with single-step defined floating gates 失效
标题翻译：具有硅化掩埋位线和单步定义浮动栅极的无契约式浮栅存储器阵列的方法
公开(公告)号：US5420060A
公开(公告)日：1995-05-30
申请号：US140410
申请日：1993-09-13
申请人： Manzur Gill , Howard L. Tigelaar
发明人： Manzur Gill , Howard L. Tigelaar
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L21/70
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。位线之间的隔离是通过厚场氧化物。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。浮动栅极的侧面由单个图案化步骤限定。所得到的结构是可编程存储器单元的密集交叉点阵列。

33. 发明授权

US5371031A Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions 失效
标题翻译：制造具有埋入式N +窗口并具有单独擦除和编程区域的EEPROM阵列的方法
公开(公告)号：US5371031A
公开(公告)日：1994-12-06
申请号：US89206
申请日：1993-07-09
申请人： Manzur Gill , Inn K. Lee
发明人： Manzur Gill , Inn K. Lee
IPC分类号： H01L21/8247 , H01L21/70
CPC分类号： H01L27/11521
摘要： An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). The source line (17) consists of alternating buried N+ windows (17a) and source regions (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). The memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) through the tunnel window (13a) to the source-line (17). The program and erase regions of the cells are physically separate from each other, and the characteristics, including the oxides, of each of those regions may be made optimum independently from each other.
摘要翻译：在半导体衬底（22）的表面上成对地形成电可擦除的电可编程的只读存储单元阵列。每个存储单元包括源极区域（11）和漏极区域（12），其间具有相应的沟道区域。福勒 - 诺德海姆隧道窗口（13a）位于连接到源（11）的源极线（17）上。源极线（17）由交替的掩埋N +窗口（17a）和源极区域（11）组成。浮动门（13）包括隧道窗部分。控制栅极（14）设置在浮置栅极（13）上，由中间层间电介质（27）绝缘。浮动栅极（13）和控制栅极（14）包括通道部分（Ch）。通道部分（Ch）用作源（11）和漏极（12）区域的自对准注入掩模，使得沟道结边缘与通道部分（Ch）的相应边缘对齐。存储单元通过从通道的热载流子注入到浮动栅极（13）进行编程，并由Fowler-Nordheim从浮动栅极（13）通过隧道窗口（13a）到源极线（17）的隧道擦除，。单元的程序和擦除区域在物理上彼此分离，并且这些区域中的每一个的特性，包括氧化物可以彼此独立地最优化。

34. 发明授权

US5051796A Cross-point contact-free array with a high-density floating-gate structure 失效
标题翻译：具有高密度浮栅结构的交叉点无接触阵列
公开(公告)号：US5051796A
公开(公告)日：1991-09-24
申请号：US403065
申请日：1989-09-01
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L27/115
CPC分类号： H01L27/115
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicated NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines having a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Bitline isolation is by P/N junction or by oxide-filled trench, permitting relatively small spacing between transistors. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：无接触式浮栅非易失性存储单元阵列和具有硅胶NSAG位线和掩埋在相对厚的氧化硅之下的源/漏区的工艺。位线具有相对较小的电阻，消除了对具有许多位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。位线隔离是通过P / N结或通过氧化物填充沟槽，允许晶体管之间的间隔相对较小。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过在控制栅极和浮置栅极之间使用具有相对较高介电常数的绝缘体来提高编程和擦除电压到浮栅的耦合。所得到的结构是可编程存储器单元的密集交叉点阵列。

35. 发明授权

US5045491A Method of making a nonvolatile memory array having cells with separate program and erase regions 失效
标题翻译：制造具有单独的程序和擦除区域的单元的非易失性存储器阵列的方法
公开(公告)号：US5045491A
公开(公告)日：1991-09-03
申请号：US589342
申请日：1990-09-28
申请人： Manzur Gill , Theodore D. Lindgren
发明人： Manzur Gill , Theodore D. Lindgren
IPC分类号： H01L21/336 , H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , H01L29/66825 , H01L29/7883 , Y10S438/981
摘要： A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first and second sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor permits programming of the cells through the first tunnelling window only and erasing of the cells through the second tunnelling window only, or vice versa.
摘要翻译：具有用于编程和擦除的分离区域的非易失性存储单元。电池在半导体本体的表面上以阵列形成，每个电池包括作为源 - 列线的一部分的源，并且包括作为漏 - 列线的一部分的漏极。每个单元在源极和漏极之间具有第一和第二子通道。每个电池单元的第一子通道的电导率由场板控制，该场板是位于第一子通道上并与第一子通道绝缘的场板 - 列 - 列线的一部分。每个第二子通道的电导率由形成在第二子通道上并与第二子通道绝缘的浮动栅极控制。每个浮动栅极具有位于相邻源极列线上方的第一隧道窗口，并且具有位于相邻排列 - 列线上方的第二隧道窗口。包括控制栅极的行线位于单元的浮动栅极的上方并与之隔绝，用于读取，编程和擦除单元。场板导体仅允许通过第一隧道窗口对单元进行编程，并且仅通过第二隧道窗口擦除单元，反之亦然。

36. 发明授权

US5017515A Process for minimizing lateral distance between elements in an integrated circuit by using sidewall spacers 失效
标题翻译：通过使用侧壁间隔来最小化集成电路中的元件之间的横向距离的方法
公开(公告)号：US5017515A
公开(公告)日：1991-05-21
申请号：US415807
申请日：1989-10-02
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/027 , H01L21/033 , H01L21/316 , H01L21/762 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11519 , H01L21/02238 , H01L21/02255 , H01L21/0271 , H01L21/033 , H01L21/31662 , H01L21/76221 , H01L27/115 , H01L27/11521
摘要： The process of this invention includes forming and patterning a first layer of photoresist to form first lines of photoresist having substantially minimum lithographic widths, forming first elements between the first lines of photoresist, removing the photoresist, forming a sidewall member on each side edge of the first elements, forming a second layer over the structure, and etching to electrically insulate the first elements and the second elements at the sidewalls. Alternatively, the structure is coated with another layer of photoresist after formation of sidewall member on each side of the first elements. The layer of photoresist is patterned to form second photoresist lines that cover alternating sidewall members. The exposed sidewall members are removed. Strips are formed between the second photoresist lines. After removal of the second photoresist lines, the structure is etched as before. However, in this embodiment, lateral extensions of the first elements are formed. The combined elements are separated by the remaining sidewall members.
摘要翻译：本发明的方法包括形成和图案化第一层光致抗蚀剂以形成具有基本最小平版印刷宽度的第一行光致抗蚀剂，在第一光致抗蚀剂线之间形成第一元件，去除光致抗蚀剂，在该光刻胶的每个侧边缘上形成侧壁部件第一元件，在结构上形成第二层，以及蚀刻以使第一元件和第二元件在侧壁处电绝缘。或者，在第一元件的每一侧上形成侧壁构件之后，该结构被另一层光致抗蚀剂涂覆。图案化光致抗蚀剂层以形成覆盖交替侧壁构件的第二光致抗蚀剂线。暴露的侧壁件被去除。在第二光致抗蚀剂线之间形成条纹。在除去第二光致抗蚀剂线之后，如前所述蚀刻结构。然而，在本实施例中，形成第一元件的横向延伸。组合的元件由剩余的侧壁构件分开。

37. 发明授权

US4994403A Method of making an electrically programmable, electrically erasable memory array cell 失效
标题翻译：制造电可编程，电可擦除存储器阵列单元的方法
公开(公告)号：US4994403A
公开(公告)日：1991-02-19
申请号：US457990
申请日：1989-12-28
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7885
摘要： A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective drain regions (30a, 30b), a shared source region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) which may be programmed by hot electron injection and erased by Fowler-Nordheim electron tunneling through respective tunneling oxide windows (40a, 40b) overlying a portion of source region (28) adjacent respective channels (38a, 38b). A wordline or control gate conductor (62) is insulatively disposed adjacent the floating gates (46a, 46b) to program or erase.
摘要翻译：在半导体层（10）的表面上形成一对电可擦除的电可编程存储器单元，并且包括各自的漏极区域（30a，30b），共享源极区域（28）和相应的沟道区域（38a，38b）。每个单元具有浮动栅极导体（46a，46b），其可以通过热电子注入来编程，并且通过Fowler-Nordheim电子隧穿通过覆盖邻近相应通道的源极区域（28）的一部分的相应隧道氧化物窗口（40a，40b）（38a，38b）。与浮动栅极（46a，46b）相邻地绝缘地布置字线或控制栅极导体（62）以进行编程或擦除。

38. 发明申请

US20060056233A1 Using a phase change memory as a replacement for a buffered flash memory 审中-公开
标题翻译：使用相变存储器作为缓冲闪存的替代品
公开(公告)号：US20060056233A1
公开(公告)日：2006-03-16
申请号：US10938705
申请日：2004-09-10
申请人： Ward Parkinson , Manzur Gill
发明人： Ward Parkinson , Manzur Gill
IPC分类号： G11C11/00 , G11C5/06
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/76 , H01L27/2427 , H01L2224/48091 , H01L2924/00014
摘要： A phase change memory may be utilized to replace NAND flash memory in combination with a buffer such as a static random access memory and/or a dynamic random access memory. Because the phase change memory may have sufficiently low cost, it may replace low cost NAND flash and because the phase change memory has sufficiently high performance, it can also replace the dynamic random access or static random access buffer memory sometimes packaged with the NAND flash memory. Thus, a relatively low cost, high performance solution is achieved in a relatively small package size in some embodiments.
摘要翻译：可以利用相变存储器来与诸如静态随机存取存储器和/或动态随机存取存储器之类的缓冲器组合地替换NAND闪速存储器。因为相变存储器可能具有足够低的成本，所以可以代替低成本的NAND闪存，并且由于相变存储器具有足够高的性能，所以它也可以替代有时与NAND闪存封装的动态随机存取或静态随机存取缓冲存储器。因此，在一些实施例中，在相对小的封装尺寸中实现了相对低成本，高性能的解决方案。

39. 发明授权

US5550772A Memory array utilizing multi-state memory cells 失效
标题翻译：使用多状态存储单元的存储器阵列
公开(公告)号：US5550772A
公开(公告)日：1996-08-27
申请号：US387171
申请日：1995-02-13
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5635 , G11C11/5642 , G11C16/24 , G11C7/18
摘要： A non-volatile memory system is disclosed which includes an array of multi-state N channel floating gate memory cells along with associated control circuitry for programming, reading and erasing the cells of the array. Small geometry single transistor memory cells are used which are capable of operating both in the enhancement and the depletion modes of operation. The associated control circuitry includes circuitry for programming selected cells of the array to one of a multiplicity of programmed states, typically four states. At least one of the programmed states results in the cell having a negative threshold voltage, relative to the source region of the cell, thereby indicating depletion mode operation, with the remaining states resulting in the cell having positive threshold voltage. The use of both polarity threshold voltages increases the voltage margin between states thereby enhancing the reliability of read/write operations. The memory read circuitry applies a positive voltage, relative to the source region of the target cell, to the word line associated with the selected cell for carrying out read operations. In addition, the read circuitry applies a negative voltage to the remaining word lines so that deselected cells which are in the same column as the selected cell do not conduct current which would interfere with the reading of the selected cell. This latter feature avoids the necessity of using large geometry split channel memory cells in order to eliminate current flow in deselected cells.
摘要翻译：公开了一种非易失性存储器系统，其包括多状态N沟道浮动栅极存储器单元的阵列以及用于对阵列的单元进行编程，读取和擦除的关联的控制电路。使用能够在增强和耗尽操作模式中操作的小型几何单晶体管存储器单元。相关联的控制电路包括用于将阵列的所选单元编程为多个编程状态之一的电路，通常为四个状态。编程状态中的至少一个导致单元相对于单元的源极区域具有负的阈值电压，从而指示耗尽模式操作，其余状态导致单元具有正的阈值电压。使用极性阈值电压会增加状态之间的电压余量，从而提高读/写操作的可靠性。存储器读取电路将相对于目标单元的源极区域的正电压施加到与所选择的单元相关联的字线，以执行读取操作。此外，读取电路对剩余字线施加负电压，使得与所选择的单元处于同一列的取消选择的单元不导通将干扰所选单元的读取的电流。后一个特征避免了使用大的几何分裂通道存储器单元以消除取消选择的单元中的电流的必要性。

40. 发明授权

US5418741A Virtual ground memory cell array 失效
标题翻译：虚拟接地存储单元阵列
公开(公告)号：US5418741A
公开(公告)日：1995-05-23
申请号：US178077
申请日：1994-01-06
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/68 , H01L29/78
CPC分类号： H01L27/11521 , H01L27/115
摘要： A memory cell array for a nonvolatile memory device having single-transistor cells (10). Row lines (15) connect the control gates of each row of cells. Column lines (17) connect the drain regions (11) and source regions (12) of columns of cells, such that pairs of row-adjacent cells share a column line (17). Each shared column line (17) has two junctions for each pair of cells that share the column line. One junction is graded for source regions (12) and the other is abrupt for drain regions (11).
摘要翻译：一种用于具有单晶体管单元（10）的非易失性存储器件的存储单元阵列。行线（15）连接每行单元格的控制门。列线（17）连接单元列的漏极区域（11）和源极区域（12），使得对相邻的行相邻单元格共享列线（17）。每个共享列线（17）对于共享列线的每对单元格具有两个连接点。对于源极区域（12），一个结点被分级，而另一个对于漏极区域（11）是突变的。

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