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31. 发明授权

US06964584B2 Low impedance, high-power socket and method of using 失效
标题翻译：低阻抗，大功率插座和使用方法
公开(公告)号：US06964584B2
公开(公告)日：2005-11-15
申请号：US10032377
申请日：2001-12-21
申请人： Dong Zhong , Yuan-Liang Li , David G. Figueroa , Jiangqi He
发明人： Dong Zhong , Yuan-Liang Li , David G. Figueroa , Jiangqi He
IPC分类号： H01R13/6466 , H01R13/6473 , H01R13/66
CPC分类号： H01R13/6625 , H01R13/6466 , H01R13/6473
摘要： The present invention relates to a power socket for a microelectronic device that, in one embodiment, uses a low-resistance power and ground terminal configuration. In another embodiment, a low-resistance power and ground terminal configuration is combined on the power socket with a vertically oriented interdigital capacitor that is used to lower inductance. By this combination a significantly lowered impedance is achieved during operation of the microelectronic device. The capacitor may include plates that are vertically oriented relative to the major planar surface of the socket faces and capacitors may be located between a power and a ground contact, between two power contacts, or between two ground contacts.
摘要翻译：本发明涉及一种用于微电子器件的电源插座，其在一个实施例中使用低电阻功率和接地端子配置。在另一个实施例中，低电阻功率和接地端子配置结合在电源插座上，并具有用于降低电感的垂直取向的交叉指状电容器。通过该组合，在微电子器件的操作期间实现显着降低的阻抗。电容器可以包括相对于插座面的主平面垂直定向的板，并且电容器可以位于电源和接地触点之间，两个电源触点之间或两个接地触点之间。

32. 发明授权

US06920051B2 Hybrid capacitor, circuit, and system 失效
标题翻译：混合电容，电路和系统
公开(公告)号：US06920051B2
公开(公告)日：2005-07-19
申请号：US10155628
申请日：2002-05-24
申请人： David G. Figueroa , Yuan-Liang Li , Huong T. Do
发明人： David G. Figueroa , Yuan-Liang Li , Huong T. Do
IPC分类号： H01L23/64 , H05K1/14 , H05K1/16 , H05K1/18
CPC分类号： H01L23/642 , H01L2924/0002 , H01L2924/15312 , H01L2924/19105 , H05K1/141 , H05K1/162 , Y10T29/435 , H01L2924/00
摘要： A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer. The discrete capacitors are electrically connected to contacts from the conductive layers to the surface of the package. During operation, one of the conductive layers of the low inductance parallel plate capacitor provides a ground plane, while the other conductive layer provides a power plane.
摘要翻译：与集成电路封装相关联的混合电容为裸片负载提供多级多余的片外电容。混合电容器包括嵌入在封装内的低电感并联板电容器，并且电连接到片外电容的第二源极。平行板电容器设置在管芯下方，并且包括顶部导电层，底部导电层和电绝缘顶层和底层的薄介电层。片外电容的第二个源是一组自对准通孔电容器和/或一个或多个分立电容器和/或附加的平行板电容器。每个自对准通孔电容器嵌入在封装内，并具有内部导体和外部导体。内部导体电连接到顶部或底部导电层，并且外部导体电连接到另一个导电层。分立电容器电连接到从导电层到封装表面的触点。在操作期间，低电感平行板电容器的导电层之一提供接地平面，而另一导电层提供电源平面。

33. 发明授权

US06900991B2 Electronic assembly with sandwiched capacitors and methods of manufacture 有权
标题翻译：带夹层电容器的电子组装及其制造方法
公开(公告)号：US06900991B2
公开(公告)日：2005-05-31
申请号：US10006292
申请日：2001-12-03
申请人： Priyavadan R. Patel , Chee-Yee Chung , David G. Figueroa , Robert L. Sankman , Yuan-Liang Li , Hong Xie , William P. Pinello
发明人： Priyavadan R. Patel , Chee-Yee Chung , David G. Figueroa , Robert L. Sankman , Yuan-Liang Li , Hong Xie , William P. Pinello
IPC分类号： H01L21/60 , H01L23/50 , H05K7/06
CPC分类号： H01L24/81 , H01L23/50 , H01L2224/16225 , H01L2224/16265 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
摘要翻译：为了提供高速，低电感电容去耦，集成电路（IC）封装包括位于管芯和IC封装衬底之间的安装区域内的电容器。各种类型和尺寸的电容器和基板可以用于各种几何布置。在一些实施例中，电容器夹在裸片端子或凸起之间以及衬底导体或衬垫之间，而在其它实施例中，电容器位于IC封装衬底的表面上的棒状导体之间。还描述了制造方法以及将包装应用于电子组件和电子系统。

34. 发明授权

US06558169B2 Shunt power connection for an integrated circuit package 有权
公开(公告)号：US06558169B2
公开(公告)日：2003-05-06
申请号：US09821699
申请日：2001-03-29
申请人： David G. Figueroa , Yuan-Liang Li , Hong Xie
发明人： David G. Figueroa , Yuan-Liang Li , Hong Xie
IPC分类号： H01R1200
CPC分类号： H01L23/50 , H01L2224/16225 , H01L2924/00014 , H01L2924/01087 , H01L2924/15312 , H01L2924/19106 , H01L2924/3011 , H05K1/0263 , H05K7/1092 , H01L2224/0401
摘要： An apparatus includes a socket and a housing. The socket and the housing can define an interior region for receiving an integrated circuit package. The housing includes a conductive member with a first portion exposed adjacent a bottom surface of the housing and a second portion at a side surface adjacent the interior region. The first portion can be electrically in contact with a printed circuit board. The second portion can be electrically in contact with a conductive member at a side surface of the integrated circuit package.

35. 发明授权

US06476477B2 Electronic assembly providing shunting of electrical current 失效
公开(公告)号：US06476477B2
公开(公告)日：2002-11-05
申请号：US09729813
申请日：2000-12-04
申请人： Yuan-Liang Li , David G. Figueroa , Priyavadan R. Patel
发明人： Yuan-Liang Li , David G. Figueroa , Priyavadan R. Patel
IPC分类号： H01L2352
CPC分类号： H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The invention provides an electronic assembly including a semiconductor chip and a semiconductor package substrate having power and ground shunts. The power and ground shunts of the semiconductor chip include contact pads on a surface thereof that are electrically connected to one another to protect electrical signal contacts on the contact pads from high, low-frequency current. The power shunt in the semiconductor package substrate connects one power plane to another and the ground shunts in the semiconductor package substrate connects one ground plane to another. The power and ground shunts in the semiconductor package substrate dictate terminal pins thereon from high, low-frequency current.

36. 发明授权

US06446317B1 Hybrid capacitor and method of fabrication therefor 失效
标题翻译：混合电容器制造方法
公开(公告)号：US06446317B1
公开(公告)日：2002-09-10
申请号：US09540705
申请日：2000-03-31
申请人： David G. Figueroa , Yuan-Liang Li , Huong T. Do
发明人： David G. Figueroa , Yuan-Liang Li , Huong T. Do
IPC分类号： H01G700
CPC分类号： H01L23/642 , H01L2924/0002 , H01L2924/15312 , H01L2924/19105 , H05K1/141 , H05K1/162 , Y10T29/435 , H01L2924/00
摘要： A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer. The discrete capacitors are electrically connected to contacts from the conductive layers to the surface of the package. During operation, one of the conductive layers of the low inductance parallel plate capacitor provides a ground plane, while the other conductive layer provides a power plane.
摘要翻译：与集成电路封装相关联的混合电容为裸片负载提供多级多余的片外电容。混合电容器包括嵌入在封装内的低电感并联板电容器，并且电连接到片外电容的第二源极。平行板电容器设置在管芯下方，并且包括顶部导电层，底部导电层和电绝缘顶层和底层的薄介电层。片外电容的第二个源是一组自对准通孔电容器和/或一个或多个分立电容器和/或附加的平行板电容器。每个自对准通孔电容器嵌入在封装内，并具有内部导体和外部导体。内部导体电连接到顶部或底部导电层，并且外部导体电连接到另一个导电层。分立电容器电连接到从导电层到封装表面的触点。在操作期间，低电感平行板电容器的导电层之一提供接地平面，而另一导电层提供电源平面。

37. 发明授权

US06366467B1 Dual-socket interposer and method of fabrication therefor 有权
公开(公告)号：US06366467B1
公开(公告)日：2002-04-02
申请号：US09540046
申请日：2000-03-31
申请人： P. R. Patel , Yuan-Liang Li , David G. Figueroa , Shamala Chickamenahalli , Huong T. Do
发明人： P. R. Patel , Yuan-Liang Li , David G. Figueroa , Shamala Chickamenahalli , Huong T. Do
IPC分类号： H05K702
CPC分类号： H05K1/141 , H01L2224/16225 , H01L2924/00014 , H01L2924/15192 , H05K1/0262 , H05K3/368 , H05K7/1092 , H05K2201/049 , H05K2201/10196 , H05K2201/10325 , H05K2201/10689 , H05K2201/10704 , H01L2224/0401
摘要： An interposer includes two separate sets of pins, and inserts into two sockets on a printed circuit board. One set of pins supplies power to a step down converter (SDC) mounted on the interposer. The second set of pins provide inputs and outputs to an integrated circuit mounted on the interposer. One or more conductive traces in or on the interposer electrically connect an output of the SDC to an input of the integrated circuit, thus supplying regulated power to the integrated circuit through the interposer. The SDC and integrated circuit can be directly mounted on the interposer, or either or both can be mounted on packages that connect to the interposer. The SDC and integrated circuit can be flip chips or can be connected to the interposer or package using wirebonds. The packages can be pinned or connectable by solder bumps.

38. 发明授权

US07535728B2 Electronic assemblies comprising ceramic/organic hybrid substrate with embedded capacitors 失效
标题翻译：电子组件包括具有嵌入式电容器的陶瓷/有机混合基板
公开(公告)号：US07535728B2
公开(公告)日：2009-05-19
申请号：US11466351
申请日：2006-08-22
申请人： Kishore K. Chakravorty , Paul H. Wermer , David G. Figueroa , Debabrata Gupta
发明人： Kishore K. Chakravorty , Paul H. Wermer , David G. Figueroa , Debabrata Gupta
IPC分类号： H05K1/18
CPC分类号： H01L23/49822 , H01L23/50 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01077 , H01L2924/01078 , H01L2924/01087 , H01L2924/09701 , H01L2924/15174 , H01L2924/3011 , H01L2924/3511 , H05K1/0231 , H05K1/0306 , H05K1/141 , H05K1/162 , H05K1/185 , H05K3/4605 , H05K3/4688 , H05K2201/0154 , H05K2201/09309 , H05K2201/10674 , H01L2224/0401
摘要： To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.
摘要翻译：为了降低开关噪声，集成电路管芯的电源端子耦合到多层陶瓷/有机混合衬底中的至少一个嵌入式电容器的相应端子。在一个实施例中，衬底的陶瓷部分包括由夹在导电平面之间的高电容率层形成的至少一个电容器。基板的有机部分包括电源和信号导体的合适布线和扇出。有机部分包括覆盖陶瓷部分的多层有机材料的堆积。还描述了电子系统，数据处理系统和各种制造方法。

39. 发明授权

US06556453B2 Electronic circuit housing with trench vias and method of fabrication therefor 有权
公开(公告)号：US06556453B2
公开(公告)日：2003-04-29
申请号：US09735956
申请日：2000-12-13
申请人： David G. Figueroa , Nicholas R. Watts
发明人： David G. Figueroa , Nicholas R. Watts
IPC分类号： H05K118
CPC分类号： H01L23/5383 , H01L23/50 , H01L23/64 , H01L24/17 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H05K1/0231 , H05K1/185 , H01L2924/00 , H01L2224/0401
摘要： An electronic circuit package (400, FIG. 4) includes one or more trench vias (404, FIG. 4). Each trench via makes electrical contact with one or more terminals (526, FIG. 5) of a discrete device (520, FIG. 5) embedded within the package. A trench via can extend to a surface of the package, or one or more conventional vias (620, FIG. 6) formed within layers (602, FIG. 6) above or below the trench via can electrically connect the trench via, and thus the discrete device, to the surface of the package. The discrete device (520, FIG. 5) can be a capacitor, in one embodiment, providing decoupling capacitance to an integrated circuit load. Besides being implemented in a package, the trench vias also could be implemented in other types of electronic circuit housings (e.g., interposers, sockets, and printed circuit boards).

40. 发明授权

US06555920B2 Vertical electronic circuit package 有权
标题翻译：垂直电子电路封装
公开(公告)号：US06555920B2
公开(公告)日：2003-04-29
申请号：US09897369
申请日：2001-07-02
申请人： Chee-Yee Chung , David G. Figueroa , Robert L. Sankman
发明人： Chee-Yee Chung , David G. Figueroa , Robert L. Sankman
IPC分类号： H01L2348
CPC分类号： H05K1/141 , H01L23/49822 , H01L23/49827 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15174 , H01L2924/15311 , H01L2924/15312 , H01L2924/19105 , H01L2924/3025 , H05K1/0231 , H05K1/0298 , H05K3/3436 , H05K3/366 , H05K2201/0919 , H05K2201/10446 , H05K2201/10454 , H05K2201/10674 , H05K2201/10719 , H01L2224/05599
摘要： An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.
摘要翻译：电子电路封装包括电连接到水平封装部分（图3的306）的垂直封装部分（304，图3）。垂直封装部分包括与垂直平面平行取向的多个导电层（512,514,516，图5）。垂直部分的水平顶面（图6中的608）上的第一组接合焊盘（606，图6）可以连接到集成电路（图6的302）的接合焊盘（602，图6）。 3）。垂直部分的水平底面（图6中的614）上的第二组接合焊盘（612，图6））可以连接到水平封装部分上的接合焊盘（616，图6）。垂直部分的导电层在第一方向上进行接合焊盘间距转换，并且水平封装部分内的导电结构（906,908,910，图9）在第二方向上执行接合焊盘间距转换。

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