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31. 发明授权

US5404473A Apparatus and method for handling string operations in a pipelined processor 失效
标题翻译：在流水线处理器中处理字符串操作的装置和方法
公开(公告)号：US5404473A
公开(公告)日：1995-04-04
申请号：US204612
申请日：1994-03-01
申请人： David B. Papworth , Michael A. Fetterman , Andrew F. Glew , Lawrence O. Smith, III , Michael M. Hancock , Beth Schultz
发明人： David B. Papworth , Michael A. Fetterman , Andrew F. Glew , Lawrence O. Smith, III , Michael M. Hancock , Beth Schultz
IPC分类号： G06F9/308 , G06F9/32 , G06F9/38 , G06F13/00
CPC分类号： G06F9/30018 , G06F9/325 , G06F9/3842
摘要： In a pipelined processor, an apparatus for handling string operations. When a string operation is received by the processor, the length of the string as specified by the programmer is stored in a register. Next, an instruction sequencer issues an instruction that computes the register value minus a pre-determined number of iterations to be issued into the pipeline. Following the instruction, the pre-determined number of iterations are issued to the pipeline. When the instruction returns with the calculated number, the instruction sequencer then knows exactly how many iterations should be executed. Any extra iterations that had initially been issued are canceled by the execution unit, and additional iterations are issued as necessary. A loop counter in the instruction sequencer is used to track the number of iterations.
摘要翻译：在流水线处理器中，用于处理字符串操作的装置。当处理器接收到字符串操作时，由编程器指定的字符串的长度存储在寄存器中。接下来，指令定序器发出计算寄存器值减去要发布到流水线中的预定数量的迭代的指令。按照该指令，将预先确定的迭代次数发布到流水线。当指令以计算出的数字返回时，指令定序器将准确地知道应该执行多少次迭代。最初发布的任何额外的迭代将被执行单元取消，并根据需要发出额外的迭代。指令定序器中的循环计数器用于跟踪迭代次数。

32. 发明授权

US06393550B1 Method and apparatus for pipeline streamlining where resources are immediate or certainly retired 失效
标题翻译：用于管道精简的方法和装置，其中资源是立即的或肯定退休的
公开(公告)号：US06393550B1
公开(公告)日：2002-05-21
申请号：US08532225
申请日：1995-09-19
申请人： Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
发明人： Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
IPC分类号： G06F930
CPC分类号： G06F9/30167 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： Maximum throughput or “back-to-back” scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.
摘要翻译：通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。这两个操作通过多种机制来实现。用于确定源操作数的可用性以及因此用于调度到可用执行单元的依赖指令的准备状态的一种机制依赖于在源操作数为退休或即时值时在分配期间早期设置源有效位。这允许保留站的就绪逻辑开始调度发送指令。

33. 发明授权

US5809325A Circuit and method for scheduling instructions by predicting future availability of resources required for execution 失效
公开(公告)号：US5809325A
公开(公告)日：1998-09-15
申请号：US676528
申请日：1996-07-09
申请人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
发明人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/384 , G06F9/30145 , G06F9/30167 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3875 , G06F9/3885 , G06F9/3889 , G06F9/3891
摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

34. 发明授权

US5842036A Circuit and method for scheduling instructions by predicting future availability of resources required for execution 失效
公开(公告)号：US5842036A
公开(公告)日：1998-11-24
申请号：US954444
申请日：1997-10-20
申请人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
发明人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/384 , G06F9/30145 , G06F9/30167 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3875 , G06F9/3885 , G06F9/3889 , G06F9/3891
摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

35. 发明授权

US5555432A Circuit and method for scheduling instructions by predicting future availability of resources required for execution 失效
标题翻译：通过预测执行所需资源的未来可用性来调度指令的电路和方法
公开(公告)号：US5555432A
公开(公告)日：1996-09-10
申请号：US293388
申请日：1994-08-19
申请人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
发明人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/384 , G06F9/30145 , G06F9/30167 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3875 , G06F9/3885 , G06F9/3889 , G06F9/3891
摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.
摘要翻译：公开了一种包括执行单元，存储单元和调度器的乱序执行处理器。存储单元存储等待执行所需资源的可用性的指令。调度器周期性地确定执行每个指令所需的资源是否可用，如果是，则将该指令分派到执行单元。执行单元在实际可用的硬件资源之前指示诸如功能单元和写回端口的硬件资源的未来可用性数个时钟周期。调度器基于硬件资源的未来可用性的指示来确定执行指令所需的资源的可用性，并且分派用于执行的指令。无序执行处理器还包括在实际完成执行之前确定源指令执行的多个时钟周期的未来完成的装置。调度器调度执行需要对操作数的这种源指令之一的执行结果的数据相关指令。一旦源指令的执行结果可用，旁路多路复用器将执行结果旁路到分派的数据相关指令中。旁路复用器将具有完全组合的操作数的数据相关指令发送到执行单元以供执行。

36. 发明授权

US5553256A Apparatus for pipeline streamlining where resources are immediate or certainly retired 失效
标题翻译：用于管道精简的设备，其中资源立即或肯定退休
公开(公告)号：US5553256A
公开(公告)日：1996-09-03
申请号：US464571
申请日：1995-06-05
申请人： Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
发明人： Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
IPC分类号： G06F9/38 , G06F9/06
CPC分类号： G06F9/30167 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.
摘要翻译：通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。这两个操作通过多种机制来实现。用于确定源操作数的可用性以及因此用于调度到可用执行单元的依赖指令的准备状态的一种机制依赖于在源操作数为退休或即时值时在分配期间早期设置源有效位。这允许保留站的就绪逻辑开始调度发送指令。

37. 发明授权

US5951670A Segment register renaming in an out of order processor 失效
标题翻译：分段寄存器在乱序处理器中重命名
公开(公告)号：US5951670A
公开(公告)日：1999-09-14
申请号：US923496
申请日：1997-09-04
申请人： Andrew F. Glew , Michael A. Fetterman
发明人： Andrew F. Glew , Michael A. Fetterman
IPC分类号： G06F9/30 , G06F15/00
CPC分类号： G06F9/30098 , G06F9/3013 , G06F9/384
摘要： A processor for executing a plurality of instructions. The processor comprises a plurality of logical segment registers, wherein the logical segment registers define an architectural state for memory segmentation of the processor. A plurality of physical segment registers are coupled to the logical segment registers. The processor further comprises an issue cluster that issues the instructions and that maps the logical segment registers, specified by the operations, to the physical segment registers to provide segment register renaming in the processor.
摘要翻译：一种用于执行多个指令的处理器。处理器包括多个逻辑段寄存器，其中逻辑段寄存器定义用于处理器的存储器分段的架构状态。多个物理段寄存器耦合到逻辑段寄存器。该处理器还包括发出指令并将由操作指定的逻辑段寄存器映射到物理段寄存器的问题簇，以在处理器中提供段寄存器重命名。

38. 发明授权

US5889982A Method and apparatus for generating event handler vectors based on both operating mode and event type 失效
标题翻译：基于操作模式和事件类型生成事件处理程序向量的方法和装置
公开(公告)号：US5889982A
公开(公告)日：1999-03-30
申请号：US498696
申请日：1995-07-01
申请人： Scott Dion Rodgers , Rohit Vidwans , Joel Huang , Michael A. Fetterman , Kamla Huck
发明人： Scott Dion Rodgers , Rohit Vidwans , Joel Huang , Michael A. Fetterman , Kamla Huck
IPC分类号： G06F9/48 , G06F9/00
CPC分类号： G06F9/4812
摘要： A method and apparatus for handling events, such as those which occur in a processor. An event vector is formed by combining event type information indicating a type of event in the processor and mode information indicating an operating mode of the processor. A microcode event handler vector is generated therefrom, for example, by referencing a lookup table. The microcode event handler vector is then used for invoking a microcode event handler to handle occurrence of these events in the processor. By the formation of an event vector, and the microcode event handler vector, execution performance is increased due to avoiding conditional branching within the processor, such as modem high performance architectures, including those which execute instructions in and out-of-order.
摘要翻译：一种处理事件的方法和装置，例如在处理器中发生的事件。通过组合指示处理器中的事件类型的事件类型信息和指示处理器的操作模式的模式信息来形成事件向量。例如，通过引用查找表来生成微代码事件处理程序向量。然后，微代码事件处理程序向量用于调用微代码事件处理程序来处理处理器中这些事件的发生。通过形成事件向量和微代码事件处理程序向量，由于避免了处理器内的条件分支，诸如调制解调器高性能体系结构（包括执行执行指令和无序执行指令）的执行性能增加。

39. 发明授权

US07941651B1 Method and apparatus for combining micro-operations to process immediate data 有权
标题翻译：用于组合微操作以处理即时数据的方法和装置
公开(公告)号：US07941651B1
公开(公告)日：2011-05-10
申请号：US10185876
申请日：2002-06-27
申请人： Bret L. Toll , John Alan Miller , Michael A. Fetterman
发明人： Bret L. Toll , John Alan Miller , Michael A. Fetterman
IPC分类号： G06F9/34
CPC分类号： G06F9/3001 , G06F9/30003 , G06F9/30145 , G06F9/30167 , G06F9/3017
摘要： A method and apparatus for combining micro-operations to process immediate data. The immediate data may be wider than the immediate data storage capacity of a micro-operation. A first micro-operation is issued to process a first portion of the immediate data, which can be processed within the immediate data storage capacity of a micro-operation. A second micro-operation is issued to process a second portion of the immediate data, which can be processed within the immediate data storage capacity of a micro-operation. Execution of the first and second micro-operations and optionally of a third micro-operation serves to reconstruct the immediate data comprising the first portion and the second portion of the immediate data.
摘要翻译：一种用于组合微操作以处理即时数据的方法和装置。即时数据可能比微操作的即时数据存储容量更宽。发出第一微操作以处理即时数据的第一部分，其可以在微操作的即时数据存储容量内处理。发出第二微操作以处理立即数据的第二部分，其可以在微操作的即时数据存储容量内处理。执行第一和第二微操作以及可选地第三微操作用于重构包括即时数据的第一部分和第二部分的即时数据。

40. 发明授权

US07103751B1 Method and apparatus for representation of an address in canonical form 有权
标题翻译：以规范形式表示地址的方法和装置
公开(公告)号：US07103751B1
公开(公告)日：2006-09-05
申请号：US10186004
申请日：2002-06-27
申请人： Bret L. Toll , John Alan Miller , Michael A. Fetterman
发明人： Bret L. Toll , John Alan Miller , Michael A. Fetterman
IPC分类号： G06F12/00
CPC分类号： G06F12/0615
摘要： A method and apparatus for representing an address in canonical form. The address is received and an error indicator is computed according to whether the address is received in a correct canonical form. The error indicator is stored together with a portion of the address, the portion being less than the entire address. The error indicator, together with the portion of the address stored, represent the address received.
摘要翻译：一种用于以规范形式表示地址的方法和装置。接收地址，并根据地址是否以正确的规范形式接收，计算错误指示符。错误指示器与地址的一部分一起存储，该部分小于整个地址。错误指示器与存储的地址部分一起表示收到的地址。

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