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    • 38. 发明授权
    • Pivotal and vertically translatable dock leveler lip
    • 垂直和垂直可翻译的水准仪唇
    • US07213285B2
    • 2007-05-08
    • US10917124
    • 2004-08-12
    • Michael Mitchell
    • Michael Mitchell
    • E01D1/00
    • B65G69/2811B65G69/2888
    • A dock leveler includes a lip that not only pivots between an extended operative position and a pendant position relative to a deck but also translates in its pendant position between blocking and non-blocking positions. A fastener connects the lip to a hinge in such a way as to minimize the stress between the fastener and the lip. The hinge includes a lip-facing surface into which the fastener is anchored, wherein the fastener is tilted out of perpendicularity to the lip-facing surface. The head of the fastener is held parallel to the lip even though an angled gap may exist between the lip and the lip-facing surface of the hinge.
    • 码头矫直机包括不仅在延伸的操作位置和相对于甲板的悬挂位置之间枢转的唇部,而且还在其阻挡位置和非阻挡位置之间的其垂直位置平移。 紧固件将唇缘连接到铰链,使得紧固件和唇缘之间的应力最小化。 铰链包括面向唇部的表面,紧固件被固定在该唇部中,其中紧固件倾斜成与唇面相对的表面垂直。 紧固件的头部平行于唇部保持,即使唇缘和铰链的面向唇的表面之间可能存在成角度的间隙。
    • 40. 发明申请
    • Systems and arrangements for promoting a line from shared to exclusive in a cache
    • 在缓存中促进从共享到独占的行的系统和安排
    • US20060212659A1
    • 2006-09-21
    • US11083615
    • 2005-03-18
    • James DieffenderferPraveen KarandikarMichael MitchellThomas SpeierPaul Steinmetz
    • James DieffenderferPraveen KarandikarMichael MitchellThomas SpeierPaul Steinmetz
    • G06F13/28G06F12/00
    • G06F12/0833
    • Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.
    • 考虑了在缓存中促进从共享到独占的系统和布置。 实施例包括高速缓存控制器,其适于确定处理器将要发出仅地址杀死请求的存储器线是否驻留在共享状态下的高速缓存行的填充缓冲器中。 如果是这样,高速缓存控制器可以将填充缓冲区标记为没有完成总线事务并且发出针对该填充缓冲区的仅地址杀死请求。 只有地址的中断请求可以发送到总线上的其他处理器,而其他处理器可以通过使存储器线的高速缓存条目无效来进行响应。 在其他处理器确认之后,总线仲裁器可以确认杀死请求,将已经在该填充缓冲器中的存储器线路推送到独占状态。 一旦被提升,填充缓冲器可以被标记为完成总线事务并且可以被写入高速缓存。