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31. 发明授权

US07930514B2 Method, system, and computer program product for implementing a dual-addressable cache 失效
标题翻译：用于实现双重寻址缓存的方法，系统和计算机程序产品
公开(公告)号：US07930514B2
公开(公告)日：2011-04-19
申请号：US11054298
申请日：2005-02-09
申请人： Norbert Hagspiel , Erwin Pfeffer , Bruce A. Wagar
发明人： Norbert Hagspiel , Erwin Pfeffer , Bruce A. Wagar
IPC分类号： G06F12/00
CPC分类号： G06F12/0864
摘要： A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. In response to a request for a primary address based upon a known secondary address corresponding to the primary address, the method also includes generating an index for the secondary address, and inserting or updating one of the indirect indices into one of the fields for a congruence class relating to the secondary address. The indirect index is assigned a value of a virtual index corresponding to the primary address. The method further includes searching congruence classes of each of the indirect indices for the secondary address.
摘要翻译：提供了一种用于实现双重寻址缓存的方法，系统和计算机程序产品。该方法包括为缓存目录中提供的每个同余类添加间接索引的字段。缓存目录由主地址索引。响应于基于对应于主地址的已知辅助地址的主地址的请求，该方法还包括生成辅助地址的索引，以及将间接索引中的一个插入或更新到一个字段中以用于一致与次要地址相关的课程。为间接索引分配与主地址相对应的虚拟索引的值。该方法还包括搜索辅助地址的每个间接索引的同余类。

32. 发明申请

US20090216516A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING TRACE DATA 失效
标题翻译：方法，用于生成跟踪数据的系统和计算机程序产品
公开(公告)号：US20090216516A1
公开(公告)日：2009-08-27
申请号：US12036430
申请日：2008-02-25
申请人： Debbie A. St. Onge , Jane H. Bartik , Barry W. Krumm , Erwin Pfeffer , Chung-Lung Kevin Shum
发明人： Debbie A. St. Onge , Jane H. Bartik , Barry W. Krumm , Erwin Pfeffer , Chung-Lung Kevin Shum
IPC分类号： G06F9/44
CPC分类号： G06F11/3466 , G06F11/3461 , G06F2201/885
摘要： There is provided a method, system and computer program product for generating trace data related to a data processing system event. The method includes: receiving an instruction relating to the system event from a location in the system; determining a minimum number of trace segment records required to record instruction information; and creating a trace segment table including the number of trace segment records, the number of trace segment records including at least one instruction record.
摘要翻译：提供了一种用于生成与数据处理系统事件相关的跟踪数据的方法，系统和计算机程序产品。该方法包括：从系统中的位置接收与系统事件有关的指令; 确定记录指令信息所需的跟踪段记录的最小数量; 并创建包括跟踪段记录的数量的跟踪段表，包括至少一个指令记录的跟踪段记录的数目。

33. 发明授权

US06766434B2 Method for sharing a translation lookaside buffer between CPUs 有权
标题翻译：在CPU之间共享翻译后备缓冲区的方法
公开(公告)号：US06766434B2
公开(公告)日：2004-07-20
申请号：US10126239
申请日：2002-04-19
申请人： Ute Gaertner , Norbert Hagspiel , Frank Lehnert , Erwin Pfeffer , Kerstin Schelm
发明人： Ute Gaertner , Norbert Hagspiel , Frank Lehnert , Erwin Pfeffer , Kerstin Schelm
IPC分类号： G06F1208
CPC分类号： G06F12/1027
摘要： The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a second-level translation lookaside buffer (TLB 2) between several CPUs (30a, . . . 30d) for improving the performance and reducing the chip area required to buffer the results of virtual-to-absolute address translations. The inventive TLB2 organization comprises several small arrays (32a, . . . 32d) dedicated to particular CPUs, providing an interface to a major array (21), which is shared between the CPUs. The dedicated arrays 32a, . . . 32d) are required to fulfill the architected constraints and link several CPUs to the commonly used shared array (21).
摘要翻译：本发明一般涉及诸如IBM ESA / 390或RS / 6000系统的共享存储器多处理器系统，更具体地涉及用于在多个CPU之间共享第二级转换后备缓冲器（TLB 2）的方法和系统（ 30a，... 30d），用于提高性能并减少缓冲虚拟到绝对地址转换结果所需的芯片面积。本发明的TLB2组织包括专用于特定CPU的几个小阵列（32a，...，32d），提供与CPU之间共享的主阵列（21）的接口。专用阵列32a，。。。 32d）需要满足架构约束并将多个CPU链接到常用的共享阵列（21）。

34. 发明授权

US08166239B2 Translation lookaside buffer and related method and program product utilized for virtual addresses 失效
标题翻译：翻译后备缓冲区以及用于虚拟地址的相关方法和程序产品
公开(公告)号：US08166239B2
公开(公告)日：2012-04-24
申请号：US12142885
申请日：2008-06-20
申请人： Matthias Fertig , Ute Gaertner , Norbert Hagspiel , Erwin Pfeffer
发明人： Matthias Fertig , Ute Gaertner , Norbert Hagspiel , Erwin Pfeffer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1036
摘要： A program product, a translation lookaside buffer and a related method for operating the TLB is provided. The method comprises the steps of: a) when adding an entry for a virtual address to said TLB testing whether the attribute data of said virtual address is already stored in said CAM and if the attribute data is not stored already in said CAM, generating tag data for said virtual address such that said tag data is different from the tag data generated for the other virtual addresses currently stored in said RAM and associated to the new entry in said CAM for the attribute data, adding the generated tag data to said RAM and to the associated entry in said CAM, and setting a validity flag in said CAM for said associated entry; else if the attribute data is stored already in said CAM, adding the stored attribute data to the entry in said RAM for said virtual address; and when performing a TLB lookup operation: reading the validity flag and the tag data from the entry in said CAM, which is associated to the entry in said RAM for said virtual address, and simultaneously reading the absolute address and the tag data from the entry in said RAM for said virtual address, and generating a TLB hit only if the tag data read from said CAM is valid and matches the tag data read from said RAM.
摘要翻译：提供了一种程序产品，翻译后备缓冲器和用于操作TLB的相关方法。该方法包括以下步骤：a）当向所述TLB添加虚拟地址的条目时，测试所述虚拟地址的属性数据是否已经存储在所述CAM中，并且属性数据是否已经存储在所述CAM中，生成标签用于所述虚拟地址的数据，使得所述标签数据不同于当前存储在所述RAM中并与所述CAM中的新条目相关联的用于属性数据的其他虚拟地址生成的标签数据，将生成的标签数据添加到所述RAM，到所述CAM中的相关联的条目，并且在所述CAM中为所述相关联的条目设置有效标志; 否则如果属性数据已经存储在所述CAM中，则将存储的属性数据添加到用于所述虚拟地址的所述RAM中的条目; 并且当执行TLB查找操作时：从与所述RAM中的所述虚拟地址的条目相关联的所述CAM中的条目读取有效性标志和标签数据，并同时从所述条目读取绝对地址和标签数据在所述RAM中用于所述虚拟地址，并且仅当从所述CAM读取的标签数据有效并且与从所述RAM读取的标签数据匹配时才产生TLB命中。

35. 发明授权

US5761734A Token-based serialisation of instructions in a multiprocessor system 失效
标题翻译：多处理器系统中基于令牌的指令序列化
公开(公告)号：US5761734A
公开(公告)日：1998-06-02
申请号：US689762
申请日：1996-08-13
申请人： Erwin Pfeffer , Klaus-Joerg Getzlaff , Ute Gaertner , Hans-Werner Tast
发明人： Erwin Pfeffer , Klaus-Joerg Getzlaff , Ute Gaertner , Hans-Werner Tast
IPC分类号： G06F9/46 , G06F12/10 , G06F12/16
CPC分类号： G06F9/52 , G06F12/1072
摘要： A process is disclosed to serialize instructions that are to be processed serially in a multiprocessor system, with the use of a token, where the token can be assigned on request to one of the processors, which thereupon has the right to execute the command. If the command consists of dristibuted tasks, the token remains blocked until the last dependent task belonging to the command has also been executed. It is only then that the token can be assigned to another instruction. Moreover, a device is described to manage this token, which features three states: a first state, in which the token is available, a second state, in which the token is assigned to one of the processors, and a third state, in which the token is blocked, because dependent tasks still have to be carried out. Moreover, a circuit is disclosed with which the token principle that is introduced can be implemented in a simple manner. The token is only available if none of the processors i is in possession of the token and if no dependent task is pending at any of the processors. The OR chaining of signals to form a signal C which is set if the token is not available represents the basic circuitry with which the serialisation of commands consisting of distributed tasks is carried out. The invention is applied particularly in the case of commands such as IPTE (invalidate page-table entry) and SSKE (set storage key extended), which modify the address translation tables in the memory that are used in common by all processors.
摘要翻译：公开了一种过程，其使用令牌来序列化要在多处理器系统中串行处理的指令，其中令牌可以根据请求分配给一个处理器，其中有一个执行命令。如果命令由dristibuted任务组成，令牌将保持阻塞，直到属于命令的最后一个任务也已被执行。只有令牌可以分配给另一个指令。此外，描述了一种用于管理该令牌的设备，其特征在于三个状态：其中令牌可用的第一状态，其中将令牌分配给处理器之一的第二状态和第三状态，其中令牌被阻止，因为依赖的任务仍然需要执行。此外，公开了可以以简单的方式实现引入的令牌原理的电路。该令牌仅在没有任何一个处理器拥有该令牌并且任何一个处理器中未依赖任务的情况下可用。如果令牌不可用，则形成信号C的OR链接形成表示执行由分散任务组成的命令的串行化的基本电路。本发明特别适用于诸如IPTE（无效页表条目）和SSKE（设置存储密钥扩展）的命令的情况，其修改由所有处理器共同使用的存储器中的地址转换表。

36. 发明授权

US4570180A Method for automatic optical inspection 失效
标题翻译：自动光学检测方法
公开(公告)号：US4570180A
公开(公告)日：1986-02-11
申请号：US498333
申请日：1983-05-26
申请人： Heinz Baier , Peter Kopp , Martin Schneiderhan , Hans-Peter Reimann , Hans Rosch , Erwin Pfeffer
发明人： Heinz Baier , Peter Kopp , Martin Schneiderhan , Hans-Peter Reimann , Hans Rosch , Erwin Pfeffer
IPC分类号： G01N21/88 , G01B11/24 , G01N21/956 , G01R31/28 , G01R31/309 , G06T7/00 , H04N7/18
CPC分类号： G06T7/001 , G01B11/24 , G01R31/2806 , G01R31/309 , G06T2207/30141 , G06T2207/30148
摘要： Method and apparatus for automatic optical inspection of a substantially two-dimensional pattern using digital image processing techniques are described. In a first processing step, all regions of a digitized stored image derived from the two-dimensional pattern are scanned for edges or lines, that is, transitions between regions having optically different characteristics. The scanned edge regions are marked in the image storage. In a subsequent second processing step all non-marked regions of the image storage are scanned and tested for the presence of permissible grey levels. A meander-shaped scanning track is used for scanning the edge or lined regions. The apparatus for implementing this method includes special latch circuitry for eliminating the further processing of marked regions, thus increasing the overall speed at which the two-dimensional pattern can be optically inspected.
摘要翻译：描述了使用数字图像处理技术对基本上二维图案进行自动光学检查的方法和装置。在第一处理步骤中，针对边缘或线扫描从二维图案导出的数字化存储的图像的所有区域，即具有光学不同特性的区域之间的转变。扫描的边缘区域被标记在图像存储器中。在随后的第二处理步骤中，图像存储器的所有未标记区域被扫描并测试是否存在允许的灰度级。曲折形扫描轨道用于扫描边缘或内衬区域。用于实现该方法的装置包括用于消除标记区域的进一步处理的特殊锁存电路，从而增加可以对二维图案进行光学检查的整体速度。

37. 发明申请

US20060179233A1 Method, system, and computer program product for implementing a dual-addressable cache 失效
标题翻译：用于实现双重寻址缓存的方法，系统和计算机程序产品
公开(公告)号：US20060179233A1
公开(公告)日：2006-08-10
申请号：US11054298
申请日：2005-02-09
申请人： Norbert Hagspiel , Erwin Pfeffer , Bruce Wagar
发明人： Norbert Hagspiel , Erwin Pfeffer , Bruce Wagar
IPC分类号： G06F12/00
CPC分类号： G06F12/0864
摘要： A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. In response to a request for a primary address based upon a known secondary address corresponding to the primary address, the method also includes generating an index for the secondary address, and inserting or updating one of the indirect indices into one of the fields for a congruence class relating to the secondary address. The indirect index is assigned a value of a virtual index corresponding to the primary address. The method further includes searching congruence classes of each of the indirect indices for the secondary address.
摘要翻译：提供了一种用于实现双重寻址缓存的方法，系统和计算机程序产品。该方法包括为缓存目录中提供的每个同余类添加间接索引的字段。缓存目录由主地址索引。响应于基于对应于主地址的已知辅助地址的主地址的请求，该方法还包括生成辅助地址的索引，以及将间接索引中的一个插入或更新到一个字段中以用于一致与次要地址相关的课程。为间接索引分配与主地址相对应的虚拟索引的值。该方法还包括搜索辅助地址的每个间接索引的同余类。

38. 发明申请

US20050273561A1 Method, system and program product for clearing selected storage translation buffer entries 有权
标题翻译：清除所选存储转换缓冲区条目的方法，系统和程序产品
公开(公告)号：US20050273561A1
公开(公告)日：2005-12-08
申请号：US11204321
申请日：2005-08-15
申请人： Timothy Siegel , Lisa Heller , Erwin Pfeffer , Kenneth Plambeck
发明人： Timothy Siegel , Lisa Heller , Erwin Pfeffer , Kenneth Plambeck
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/30047 , G06F9/3824 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/683
摘要： An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
摘要翻译：提供指令来执行与特定地址空间相关联的所选地址转换缓冲器条目（TLB条目）的清除，诸如存储段或存储区域。缓冲区条目与段表项或区域表项或ASCE地址相关。该指令可以通过软件仿真，硬件，固件或其组合来实现。

39. 发明申请

US20050268045A1 Method, system and program product for invalidating a range of selected storage translation table entries 有权
标题翻译：用于使选定的存储转换表项的范围无效的方法，系统和程序产品
公开(公告)号：US20050268045A1
公开(公告)日：2005-12-01
申请号：US11199666
申请日：2005-08-09
申请人： Timothy Slegel , Lisa Heller , Erwin Pfeffer , Kenneth Plambeck
发明人： Timothy Slegel , Lisa Heller , Erwin Pfeffer , Kenneth Plambeck
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/30047 , G06F9/3824 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/683
摘要： Selected units of storage, such as segments of storage or regions of storage, may be invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage may be cleared. An instruction is provided to perform the invalidation and clearing. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
摘要翻译：所选存储单元（如存储区域或存储区域）可能无效。通过设置位于与要被无效的存储单元相对应的数据结构条目中的无效指示符来促进无效。此外，可以清除与无效的存储单元或其他所选择的存储单元相关联的缓冲器条目。提供了执行无效和清除的指令。该指令可以通过软件仿真，硬件，固件或其组合来实现。

40. 发明授权

US06694344B1 Examination of residues of data-conversions 失效
标题翻译：检查数据转换的残留
公开(公告)号：US06694344B1
公开(公告)日：2004-02-17
申请号：US09436851
申请日：1999-11-09
申请人： Guenter Gerwig , Juergen Haess , Michael Kroener , Erwin Pfeffer
发明人： Guenter Gerwig , Juergen Haess , Michael Kroener , Erwin Pfeffer
IPC分类号： G06F1100
CPC分类号： G06F11/085 , G06F7/72 , H03M7/02
摘要： A process is provided for monitoring the conversion of numerical values from a first to a second format, where before and after the conversion, the modulo residue of the corresponding numerical value is calculated and compared with the corresponding residue after the conversion. In this way it is possible to effect error-free monitoring of such a conversion, especially of computer data, without great hardware expenditure.
摘要翻译：提供了用于监视从第一格式到第二格式的数值的转换的过程，其中在转换之前和之后，计算相应数值的模余数并将其与转换后的相应残差进行比较。以这种方式，可以在没有很好的硬件支出的情况下，对这种转换，特别是计算机数据进行无差错监视。

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