专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07700999B2 SRAM device 有权
标题翻译： SRAM器件
公开(公告)号：US07700999B2
公开(公告)日：2010-04-20
申请号：US11773510
申请日：2007-07-05
申请人： Thomas Schulz
发明人： Thomas Schulz
IPC分类号： H01L23/62
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/0207 , H01L27/11 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device has a base area defining a longitudinal axis. Four in-line transistors, which are NMOS transistors in exemplary embodiments, are each centered on the longitudinal axis. Two off-set transistors, which are PMOS transistors in exemplary embodiments, are off-set to first and second sides of the longitudinal axis, respectively.
摘要翻译：集成电路器件具有限定纵轴的基区。在示例性实施例中是NMOS晶体管的四个在线晶体管每个以纵轴为中心。在示例性实施例中，PMOS晶体管的两个偏置晶体管分别偏离纵轴的第一和第二侧。

32. 发明授权

US07678632B2 MuGFET with increased thermal mass 有权
标题翻译： MuGFET具有增加的热质量
公开(公告)号：US07678632B2
公开(公告)日：2010-03-16
申请号：US11561170
申请日：2006-11-17
申请人： Harald Gossner , Christian Russ , Jens Schneider , Thomas Schulz
发明人： Harald Gossner , Christian Russ , Jens Schneider , Thomas Schulz
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L23/367 , H01L27/0248 , H01L29/66795 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed.
摘要翻译：本文讨论的一些实施例包括具有源极区域，漏极区域和翅片阵列的半导体，其可操作地耦合到栅极区域，以控制流过源极区域和漏极区域之间的鳍片的电流。所述半导体还具有至少一部分形成有至少部分热容量等于或大于所述源极区域，漏极区域和散热片阵列的热容量的冷却元件的冷却元件，所述冷却元件处于闭合状态靠近与阵列的鳍片，源极区域和漏极区域电隔离的翅片阵列的翅片。还公开了其他实施例。

33. 发明申请

US20090114955A1 Method for Fabricating a Fin-Shaped Semiconductor Structure and a Fin-Shaped Semiconductor Structure 有权
标题翻译：制造鳍形半导体结构和鳍形半导体结构的方法
公开(公告)号：US20090114955A1
公开(公告)日：2009-05-07
申请号：US11934665
申请日：2007-11-02
申请人： Chris Stapelmann , Thomas Schulz
发明人： Chris Stapelmann , Thomas Schulz
IPC分类号： H01L29/04 , H01L21/20 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/045 , H01L29/66795 , H01L29/7843 , H01L29/7845 , H01L29/785
摘要： A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction of the fin.
摘要翻译：鳍状结构由半导体材料形成。处理鳍状结构以沿着翅片的纵向方向在半导体材料内产生拉伸应变。

34. 发明申请

US20090008707A1 SRAM DEVICE 有权
标题翻译： SRAM设备
公开(公告)号：US20090008707A1
公开(公告)日：2009-01-08
申请号：US11773510
申请日：2007-07-05
申请人： Thomas Schulz
发明人： Thomas Schulz
IPC分类号： H01L27/11 , H01L29/732
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/0207 , H01L27/11 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device has a base area defining a longitudinal axis. Four in-line transistors, which are NMOS transistors in exemplary embodiments, are each centered on the longitudinal axis. Two off-set transistors, which are PMOS transistors in exemplary embodiments, are off-set to first and second sides of the longitudinal axis, respectively.
摘要翻译：集成电路器件具有限定纵轴的基区。在示例性实施例中是NMOS晶体管的四个在线晶体管每个以纵轴为中心。在示例性实施例中，PMOS晶体管的两个偏置晶体管分别偏离纵轴的第一和第二侧。

35. 发明授权

US07462538B2 Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials 有权
标题翻译：制造具有不同栅极电介质材料的多栅极CMOS晶体管的方法
公开(公告)号：US07462538B2
公开(公告)日：2008-12-09
申请号：US11273747
申请日：2005-11-15
申请人： Hong-Jyh Li , Thomas Schulz
发明人： Hong-Jyh Li , Thomas Schulz
IPC分类号： H01L21/336 , H01L29/80
CPC分类号： H01L21/823857 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/66795 , H01L29/785 , H01L29/78645
摘要： Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.
摘要翻译：公开了具有不同栅介电材料的晶体管的半导体器件及其制造方法。一个实施例包括包括工件的半导体器件，所述工件包括第一区域和靠近第一区域的第二区域。第一晶体管设置在工件的第一区域中，第一晶体管具有至少两个第一栅电极。第一栅极电介质设置在所述至少两个第一栅电极中的每一个附近，所述第一栅极电介质包括第一材料。第二晶体管设置在工件的第二区域中，第二晶体管具有至少两个第二栅电极。第二栅极电介质设置在所述至少两个第二栅电极中的每一个附近，所述第二栅极电介质包括第二材料。第二种材料与第一种材料不同。

36. 发明申请

US20080111163A1 FIELD EFFECT TRANSISTOR WITH A FIN STRUCTURE 有权
标题翻译：具有结构的场效应晶体管
公开(公告)号：US20080111163A1
公开(公告)日：2008-05-15
申请号：US11559656
申请日：2006-11-14
申请人： Christian Russ , Harald Gossner , Thomas Schulz
发明人： Christian Russ , Harald Gossner , Thomas Schulz
IPC分类号： H01L21/336 , H01L29/78 , H01L29/812 , H01L21/338 , H01L21/44
CPC分类号： H01L29/785 , H01L29/458 , H01L29/66795 , H01L29/7854 , H01L29/78621
摘要： A field effect transistor with a fin structure having a first and a second source/drain region; a body region formed within the fin structure and between the first and the second source/drain region; a metallically conductive region formed within a part of the first source/drain region, the metallically conductive region being adjacent to the body region or to a lightly doped region disposed between the body region and the first source/drain region; and a current ballasting region formed within a part of the second source/drain region.
摘要翻译：一种具有鳍结构的场效应晶体管，具有第一和第二源极/漏极区域; 形成在所述鳍结构内并且在所述第一和第二源极/漏极区之间的体区; 形成在所述第一源极/漏极区域的一部分内的金属导电区域，所述金属导电区域邻近所述体区域或者设置在所述体区域和所述第一源极/漏极区域之间的轻掺杂区域; 以及形成在第二源极/漏极区域的一部分内的电流镇流区域。

37. 发明申请

US20080038888A1 INTEGRATED CIRCUIT ARRANGEMENT WITH CAPACITOR AND FABRICATION METHOD 有权
标题翻译：集成电路与电容器和制造方法的布置
公开(公告)号：US20080038888A1
公开(公告)日：2008-02-14
申请号：US11862640
申请日：2007-09-27
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。厚的绝缘区域比控制电极绝缘区域厚。控制电极含有与远电极区域相同的材料。

38. 发明授权

US07310561B2 Identifying critical operations of a production process 有权
标题翻译：识别生产过程的关键操作
公开(公告)号：US07310561B2
公开(公告)日：2007-12-18
申请号：US11094776
申请日：2005-03-30
申请人： Sonja Barnet , Hans-Juergen Biegler , Thomas Engelmann , Matthias Gressler , Thorsten Kulick , Bernhard Lokowandt , Thomas Schulz
发明人： Sonja Barnet , Hans-Juergen Biegler , Thomas Engelmann , Matthias Gressler , Thorsten Kulick , Bernhard Lokowandt , Thomas Schulz
IPC分类号： G06F19/00
CPC分类号： G06Q10/06 , G06Q10/0631
摘要： Identifying an operation that is critical to meeting a due date of a production order includes identifying operations associated with the production order, obtaining schedules for the operations using infinite production planning, obtaining start intervals for the operations based on the schedules, selecting a target operation from the operations, and determining whether the target operation is critical to meeting the due date based on whether the target operation can be scheduled, using finite production planning, in a start interval obtained for the target operation.
摘要翻译：识别对于满足生产订单的到期日至关重要的操作包括识别与生产订单相关联的操作，使用无限生产计划获取操作的计划，基于计划获取操作的开始间隔，从并且基于在目标操作获得的开始间隔中是否可以使用有限生产计划来调整目标操作来确定目标操作是否关键到达到期日。

39. 发明授权

US07173302B2 Integrated circuit arrangement having capacitors and having planar transistors and fabrication method 有权
标题翻译：具有电容器并具有平面晶体管和制造方法的集成电路装置
公开(公告)号：US07173302B2
公开(公告)日：2007-02-06
申请号：US10531493
申请日：2003-10-10
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/1085 , H01L21/84 , H01L27/10805 , H01L27/1203
摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.
摘要翻译：描述了一种集成电路装置及其制造方法。集成电路装置包含形成电容器的绝缘区域和一系列区域。该序列包含靠近绝缘区域的近电极区域，电介质区域和远离绝缘区域的远程电极区域。绝缘区域是布置在平面中的绝缘层的一部分。电容器和有源部件布置在绝缘层的同一侧上并形成存储单元。组件的近电极区域和有源区域被布置在与布置绝缘层的平面平行的平面中。处理器也包含在集成电路装置中。

40. 发明申请

US20060271420A1 System and method for performing capacity checks and resource scheduling within a supply chain management system 审中-公开
标题翻译：在供应链管理系统内执行容量检查和资源调度的系统和方法
公开(公告)号：US20060271420A1
公开(公告)日：2006-11-30
申请号：US11140665
申请日：2005-05-27
申请人： Peter Anselmann , Stefan Siebert , Stefan Wedner , Tesfaldet Negash , Thomas Engelmann , Thomas Schulz , Thorsten Kulick , Tobias Scheuer , Volkmar Soehner , Anton Forstreuter , Bernhard Lokowandt , Christian Fuhlbruegge , Chrstian Embacher , Daniel Booss , Hans-Juergen Biegler , Heinrich Braun , Jan Osternmeier , Joachim Altmeyer
发明人： Peter Anselmann , Stefan Siebert , Stefan Wedner , Tesfaldet Negash , Thomas Engelmann , Thomas Schulz , Thorsten Kulick , Tobias Scheuer , Volkmar Soehner , Anton Forstreuter , Bernhard Lokowandt , Christian Fuhlbruegge , Chrstian Embacher , Daniel Booss , Hans-Juergen Biegler , Heinrich Braun , Jan Osternmeier , Joachim Altmeyer
IPC分类号： G06F15/02
CPC分类号： G06Q10/087 , G06Q10/06314
摘要： A system and method are described for performing bucket-oriented capacity checks on resources to determine whether activities can be processed prior to a desired delivery date. For example, a method according to one embodiment of the invention comprises: subdividing a supply chain scheduling timeline for a particular resource into a plurality of time-buckets, each of the time buckets having a specified time period and a specified total capacity supply, the total capacity supply comprising utilized capacity supply which has been consumed by previously-scheduled activities and unutilized capacity supply which is available for processing new activities; in response to receiving a customer request for a specified activity to be completed by a desired date, determining if sufficient unutilized capacity supply exists within one of the time-buckets prior to the desired date; scheduling the specified activity on the resource within the time period defined by a particular time-bucket if sufficient unutilized capacity exists within the time-bucket; and reducing the unutilized capacity by an amount of capacity supply consumed by the specified activity.
摘要翻译：描述了一种系统和方法，用于对资源执行面向桶的容量检查，以确定是否可以在期望的交付日期之前处理活动。例如，根据本发明的一个实施例的方法包括：将特定资源的供应链调度时间线细分为多个时间桶，每个时间段具有指定的时间段和指定的总容量供应，总容量供应包括利用以前计划的活动消耗的能力供应和可用于处理新活动的未使用能力供应; 响应于接收到要在期望日期完成的指定活动的客户请求，确定在期望日期之前的一个时间段内是否存在足够的未使用容量供应; 在时间段内存在足够的未使用容量的情况下，在由特定时间段定义的时间段内调度资源上的指定活动; 并通过指定活动消耗的能力供应量减少未使用的能力。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式