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31. 发明申请

US20080301376A1 Method, Apparatus, and System Supporting Improved DMA Writes 审中-公开
标题翻译：方法，设备和系统支持改进的DMA写入
公开(公告)号：US20080301376A1
公开(公告)日：2008-12-04
申请号：US11756039
申请日：2007-05-31
申请人： Brian D. Allison , David A. Shedivy , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , David A. Shedivy , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array. In response to acquiring coherency ownership, this low latency array is updated to a coherency state signifying coherency ownership by the memory controller. In a pipelined array access, both the low latency array and the second array are accessed and if the lower latency second array indicates the particular coherency state with no collision indication, the memory controller signals that the particular DMA write operation can be performed, where the signaling occurs prior to results being obtained from the higher latency first array at the normal end of the array access pipeline. In response to the signaling, the memory controller performs an update to the memory subsystem indicated by the particular DMA write operation.
摘要翻译：存储器控制器接收DMA写操作流并将其排入队列中，执行先进先出（FIFO）顺序。在处理特定DMA写入操作之前，存储器控制器获取目标存储器块的一致性所有权并将结果存储在低延迟数组中。响应于获取一致性所有权，该低延迟阵列被更新为表示存储器控制器的一致性所有权的一致性状态。在流水线阵列访问中，访问低延迟阵列和第二阵列，并且如果较低等待时间的第二阵列指示没有冲突指示的特定一致性状态，则存储器控制器指示可以执行特定的DMA写操作，其中信号发生在从阵列访问管道的正常端的较高等待时间第一阵列获得的结果之前。响应于信令，存储器控制器对由特定DMA写操作指示的存储器子系统进行更新。

32. 发明申请

US20080244190A1 Method, Apparatus, System and Program Product Supporting Efficient Eviction of an Entry From a Central Coherence Directory 审中-公开
标题翻译：方法，设备，系统和程序产品支持从中央一致性目录中有效地排除条目
公开(公告)号：US20080244190A1
公开(公告)日：2008-10-02
申请号：US11693864
申请日：2007-03-30
申请人： David A. Shedivy , Brian T. Vanderpool
发明人： David A. Shedivy , Brian T. Vanderpool
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F2212/507
摘要： In response to a memory access request missing in a central coherence directory of a data processing system, the central coherence directory issues a back-invalidate request and provides an indication of one or more processors possibly caching a copy of a victim memory block associated with a victim memory address. In response to the back-invalidate request, a memory controller initiates a lookup of coherency information for the victim memory address in the central coherence directory and, prior to receipt of the coherency information, speculatively issues a set of back-invalidate commands on one or more of multiple processor buses to invalidate any cached copy of the victim memory block. In response to receipt of the coherency information, the memory controller determines whether the set of speculatively issued back-invalidate commands was under-inclusive, and if not, removes a victim entry associated with the victim memory address from the central coherence directory.
摘要翻译：响应于在数据处理系统的中央一致性目录中丢失的存储器访问请求，中央一致目录发出无效请求，并提供一个或多个处理器的指示，可能缓存与一个或多个相关联的受害者存储器块的副本受害者内存地址。响应于反向无效请求，存储器控制器启动对中心一致目录中的受害者存储器地址的一致性信息的查找，并且在接收到一致性信息之前，推测性地在一个或多个更多的多处理器总线使受害者内存块的任何缓存副本无效。响应于一致性信息的接收，存储器控制器确定该推测发出的反向无效命令是否是不足的，如果不是，则从中央一致性目录去除与受害者存储器地址相关联的受害者条目。

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