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31. 发明授权

US5965461A Controlled linewidth reduction during gate pattern formation using a spin-on barc 失效
标题翻译：使用旋转棒条在栅极图案形成期间的受控线宽减小
公开(公告)号：US5965461A
公开(公告)日：1999-10-12
申请号：US905109
申请日：1997-08-01
申请人： Chih-Yuh Yang , Scott A. Bell , Daniel Steckert
发明人： Chih-Yuh Yang , Scott A. Bell , Daniel Steckert
IPC分类号： H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/302
CPC分类号： H01L21/28123 , H01L21/31138 , H01L21/32139 , Y10S438/952
摘要： A gate is formed by depositing a gate conductive layer over a substrate layer, depositing an organic spin-on bottom anti-reflective coating (BARC) over the gate conductive layer, and forming a resist mask on the BARC. Next, the resist mask is controllably etched to further reduce the critical dimensions of gate pattern formed therein, and then the gate is formed by etching the gate conductive layer using the reduced size resist mask.
摘要翻译：通过在衬底层上沉积栅极导电层，在栅极导电层上沉积有机旋涂底部抗反射涂层（BARC）并在BARC上形成抗蚀剂掩模来形成栅极。接下来，可控地蚀刻抗蚀剂掩模，以进一步减小其中形成的栅极图案的临界尺寸，然后通过使用减小尺寸的抗蚀剂掩模蚀刻栅极导电层来形成栅极。

32. 发明授权

US06660645B1 Process for etching an organic dielectric using a silyated photoresist mask 有权
标题翻译：使用硅化光致抗蚀剂掩模蚀刻有机电介质的方法
公开(公告)号：US06660645B1
公开(公告)日：2003-12-09
申请号：US10051725
申请日：2002-01-17
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H07L21302
CPC分类号： H01L21/31144
摘要： A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.
摘要翻译：用于形成半导体器件的工艺可以包括在衬底上形成有机电介质层，在有机介电层上形成保护层，在保护层上形成光致抗蚀剂掩模，并使光刻胶掩模进行硅化。使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻保护层，然后使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻有机介电层。金属可以沉积在蚀刻在有机介电层中的空隙中以形成布线，接触或通孔。

33. 发明授权

US07052921B1 System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process 有权
标题翻译：使用原位散射法在光刻过程中检测光致抗蚀剂图案完整性的系统和方法
公开(公告)号：US07052921B1
公开(公告)日：2006-05-30
申请号：US10934192
申请日：2004-09-03
申请人： Marina V. Plat , Bhanwar Singh , Calvin T. Gabriel , Christopher F. Lyons , Scott A. Bell , Ramkumar Subramanian , Srikanteswara Dakshina-Murthy
发明人： Marina V. Plat , Bhanwar Singh , Calvin T. Gabriel , Christopher F. Lyons , Scott A. Bell , Ramkumar Subramanian , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21/66
CPC分类号： G03F7/70625 , G03F7/70608 , H01L22/12
摘要： The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap. Another aspect of the present invention allows for a feedback control mechanism to alter a physical parameter of the photolithographic process based upon the in situ scatterometry measurements.
摘要翻译：本发明使用原位散射法来确定晶片上是否存在缺陷（例如，光致抗蚀剂侵蚀，光致抗蚀剂弯曲和图案崩溃）。在一个实施例中，原位散射法用于检测与光致抗蚀剂层相关联的图案完整性缺陷。原位散射法产生与光致抗蚀剂图案掩模的厚度相关的衍射数据。将该数据与与合适的光致抗蚀剂厚度相关联的衍射数据的模型进行比较。如果测量的衍射数据在可接受的范围内，则进行光刻工艺的下一步骤。然而，如果测量的厚度在合适的范围之外，则检测到缺陷，并且可以在主蚀刻之前将晶片发送用于再加工或重新图案化，从而防止不必要的晶片废料。本发明的另一方面允许反馈控制机制基于原位散射测量来改变光刻工艺的物理参数。

34. 发明授权

US06635409B1 Method of strengthening photoresist to prevent pattern collapse 有权
标题翻译：加强光致抗蚀剂以防止图案塌陷的方法
公开(公告)号：US06635409B1
公开(公告)日：2003-10-21
申请号：US09902568
申请日：2001-07-12
申请人： Christopher F. Lyons , Scott A. Bell , Todd Lukanc , Marina V. Plat
发明人： Christopher F. Lyons , Scott A. Bell , Todd Lukanc , Marina V. Plat
IPC分类号： G03F700
CPC分类号： G03F7/40 , G03F7/2024
摘要： There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then treated to change its material properties before the photoresist layer is dried. Also provided are a semiconductor fabrication method employing a treated photoresist and a composition for a treatable photoresist.
摘要翻译：提供了一种形成光刻应用的光致抗蚀剂层的方法，其具有增加的结构强度。光致抗蚀剂层通过掩模曝光并显影。然后在光致抗蚀剂层干燥之前，处理光致抗蚀剂层以改变其材料性质。还提供了使用经处理的光致抗蚀剂和用于可处理光致抗蚀剂的组合物的半导体制造方法。

35. 发明授权

US06541360B1 Bi-layer trim etch process to form integrated circuit gate structures 有权
标题翻译：双层微调蚀刻工艺形成集成电路门结构
公开(公告)号：US06541360B1
公开(公告)日：2003-04-01
申请号：US09845649
申请日：2001-04-30
申请人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
发明人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： H01L213205
CPC分类号： H01L21/0338 , H01L21/0271 , H01L21/0337 , H01L21/32139 , Y10S438/947 , Y10S438/952
摘要： A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of organic underlayer. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or the aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
摘要翻译：用于形成集成电路栅极结构的双层修剪蚀刻工艺可以包括在多晶硅层上沉积有机底层，在有机底层上沉积成像层，图案化成像层，选择性地修整蚀刻有机底层以形成图案，以及使用由有机底层的去除部分形成的图案去除多晶硅层的部分。因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用微调蚀刻技术，而不会有抗蚀剂侵蚀或长宽比图案崩溃的风险。这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

36. 发明授权

US06383952B1 RELACS process to double the frequency or pitch of small feature formation 失效
标题翻译： RELACS过程将小特征形成的频率或间距加倍
公开(公告)号：US06383952B1
公开(公告)日：2002-05-07
申请号：US09794632
申请日：2001-02-28
申请人： Ramkumar Subramanian , Bhanwar Singh , Marina V. Plat , Christopher F. Lyons , Scott A. Bell
发明人： Ramkumar Subramanian , Bhanwar Singh , Marina V. Plat , Christopher F. Lyons , Scott A. Bell
IPC分类号： H01L2131
CPC分类号： H01L21/0271 , H01L21/0273 , H01L21/0332 , H01L21/0337 , H01L21/0338
摘要： A method of doubling the frequency of small pattern formation. The method includes forming a photoresist layer, and then patterning it. A RELACS polymer is spread over the patterned photoresist layer. Portions of the RELACS polymer on top portions of each patterned photoresist region are removed, by either etching or by polishing them off. Portions between each patterned photoresist region are also removed in this step. The patterned photoresist regions are removed, preferably by a flood exposure and then application of a developer to the exposed photoresist regions. The remaining RELACS polymer regions, which were disposed against respective sidewalls of the patterned photoresist regions, prior to their removal, are then used for forming small pattern regions to be used in a semiconductor device to be formed on the substrate. These small pattern regions can be used to form separate poly-gates.
摘要翻译：一种将图案形成加倍的方法。该方法包括形成光致抗蚀剂层，然后对其进行图案化。 RELACS聚合物分散在图案化的光致抗蚀剂层上。通过蚀刻或通过抛光，去除每个图案化的光致抗蚀剂区域的顶部上的部分RELACS聚合物。在该步骤中也去除了每个图案化的光致抗蚀剂区域之间的部分。去除图案化的光致抗蚀剂区域，优选通过暴露曝光，然后将显影剂施加到曝光的光致抗蚀剂区域。然后将其去除之前设置在图案化光致抗蚀剂区域的相应侧壁上的剩余RELACS聚合物区域用于形成待用于形成在衬底上的半导体器件中的小图案区域。这些小图案区域可用于形成单独的多门。

37. 发明授权

US6121123A Gate pattern formation using a BARC as a hardmask 失效
标题翻译：使用BARC作为硬掩模的栅格图案形成
公开(公告)号：US6121123A
公开(公告)日：2000-09-19
申请号：US924573
申请日：1997-09-05
申请人： Christopher F. Lyons , Scott A. Bell , Olov Karlsson
发明人： Christopher F. Lyons , Scott A. Bell , Olov Karlsson
IPC分类号： G03F7/09 , H01L21/027 , H01L21/28 , H01L21/3213 , H01L21/3205 , H01L21/4763
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/28123 , H01L21/32139 , Y10S438/952
摘要： A gate is formed on a semiconductor substrate by using a SiON film as both a bottom anti-reflective coating (BARC) and subsequently as a hardmask to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, and a SiON film over the conductive layer. The resist mask is formed on the SiON film. The SiON film improves the resist mask formation process and then serves as a hardmask during subsequent etching processes. Then the wafer stack is shaped to form one or more polysilicon gates by sequentially etching through selected portions of the SiON film and the gate conductive layer as defined by the etch windows in the original resist mask. Once the gate has been properly shaped, any remaining portions of either the resist mask or the SiON film are then removed.
摘要翻译：通过使用SiON膜作为底部抗反射涂层（BARC）并随后作为硬掩模在半导体衬底上形成栅极，以更好地控制通过深UV抗蚀剂掩模定义的栅极的临界尺寸（CD）形成在其上。晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层和导电层上的SiON膜。在SiON膜上形成抗蚀剂掩模。 SiON膜改善了抗蚀剂掩模形成过程，然后在随后的蚀刻工艺中用作硬掩模。然后通过依次蚀刻由原始抗蚀剂掩模中的蚀刻窗口所限定的SiON膜和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。一旦浇口已正确成型，然后除去抗蚀剂掩模或SiON膜的任何剩余部分。

38. 发明授权

US07122455B1 Patterning with rigid organic under-layer 有权
标题翻译：图案与刚性有机底层
公开(公告)号：US07122455B1
公开(公告)日：2006-10-17
申请号：US10790567
申请日：2004-03-01
申请人： Christopher F. Lyons , Marina V. Plat , Srikanteswara Dakshina-Murthy , Scott A. Bell , Cyrus E. Tabery
发明人： Christopher F. Lyons , Marina V. Plat , Srikanteswara Dakshina-Murthy , Scott A. Bell , Cyrus E. Tabery
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28035 , H01L21/28123 , Y10S438/942 , Y10S438/947
摘要： For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.
摘要翻译：为了图案化IC（集成电路）材料，在IC材料之上形成刚性有机底层，并且将刚性有机底层图案化以形成刚性有机掩模结构。此外，修剪刚性有机掩模结构以降低刚性有机掩模结构的临界尺寸超出传统BARC掩模结构的限制。不会在刚性有机掩模结构下面的IC材料的任何部分被蚀刻掉以形成IC结构。

39. 发明授权

US06737222B2 Dual damascene process utilizing a bi-layer imaging layer 有权
标题翻译：双镶嵌工艺利用双层成像层
公开(公告)号：US06737222B2
公开(公告)日：2004-05-18
申请号：US09884834
申请日：2001-06-19
申请人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Scott A. Bell
发明人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Scott A. Bell
IPC分类号： G03F700
CPC分类号： H01L21/76829 , G03F7/0035 , G03F7/095 , H01L21/0274 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76808 , H01L2221/1031
摘要： A method of utilizing a multilayer photoresist to form contact holes and/or conductors utilizing a dual damascene process includes utilizing layered photoresists. A contact in a conductive line can be formed in a single deposition step or in a two-stage deposition step. Image layers can remain as part of the interconnect structure or be removed by a polishing technique. The process can be utilized for any conductive structures provided above a substrate of an integrated circuit.
摘要翻译：利用多层光刻胶形成接触孔和/或使用双镶嵌工艺的导体的方法包括利用层状光致抗蚀剂。可以在单个沉积步骤中或在两级沉积步骤中形成导电线中的接触。图像层可以保留为互连结构的一部分，或者通过抛光技术去除。该方法可用于设置在集成电路的衬底上的任何导电结构。

40. 发明授权

US5963841A Gate pattern formation using a bottom anti-reflective coating 失效
标题翻译：使用底部抗反射涂层的栅格图案形成
公开(公告)号：US5963841A
公开(公告)日：1999-10-05
申请号：US924370
申请日：1997-09-05
申请人： Olov B. Karlsson , Christopher F. Lyons , Minh Van Ngo , Scott A. Bell , David K. Foote
发明人： Olov B. Karlsson , Christopher F. Lyons , Minh Van Ngo , Scott A. Bell , David K. Foote
IPC分类号： H01L21/3213 , H01L21/302
CPC分类号： H01L21/32139
摘要： A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, a SiON BARC over the conductive layer, a thin oxide film over the SiON BARC. The resist mask is formed on the oxide film. The SiON BARC improves the resist mask formation process. The wafer stack is then shaped to form one or more polysilicon gates by sequentially etching through selected portions of the oxide film, the BARC, and the gate conductive layer as defined by the etch windows in the resist mask. Once properly shaped, the remaining portions of the resist mask, oxide film and SiON BARC are removed.
摘要翻译：通过使用底部抗反射涂层（BARC）在半导体衬底上形成栅极以更好地控制通过形成在其上的深UV抗蚀剂掩模所限定的栅极的临界尺寸（CD）。晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层，导电层上的SiON BARC，SiON BARC上的薄氧化物膜。在氧化物膜上形成抗蚀剂掩模。 SiON BARC改进了抗蚀剂掩模形成过程。然后通过依次蚀刻通过抗蚀剂掩模中由蚀刻窗口限定的氧化膜，BARC和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。一旦适当成形，就去除了抗蚀剂掩模，氧化膜和SiON BARC的其余部分。

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