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31. 发明授权

US07858438B2 Semiconductor device, chip package and method of fabricating the same 有权
标题翻译：半导体器件，芯片封装及其制造方法
公开(公告)号：US07858438B2
公开(公告)日：2010-12-28
申请号：US11762507
申请日：2007-06-13
申请人： Chien-Ru Chen , Ying-Lieh Chen
发明人： Chien-Ru Chen , Ying-Lieh Chen
IPC分类号： H01L21/00
CPC分类号： H01L24/10 , H01L23/525 , H01L24/13 , H01L2224/023 , H01L2224/0401 , H01L2224/05572 , H01L2224/13 , H01L2224/13023 , H01L2224/13099 , H01L2224/1411 , H01L2924/0002 , H01L2924/01005 , H01L2924/14 , H01L2924/30107 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed.
摘要翻译：半导体器件具有芯片，第一凸块电极，导线和第二凸起电极。芯片具有至少一个接触焊盘，并且第一凸块电极形成在接触焊盘上。导线布置在芯片的有源表面上并电连接到第一凸块电极。第二凸起电极形成在导线上，第二凸块电极不设置在芯片的任何接触焊盘上。此外，还公开了一种封装芯片和IC封装的方法。

32. 发明申请

US20100315396A1 TIMING CONTROLLER, DISPLAY AND CHARGE SHARING FUNCTION CONTROLLING METHOD THEREOF 审中-公开
标题翻译：时序控制器，显示和充电共享功能的控制方法
公开(公告)号：US20100315396A1
公开(公告)日：2010-12-16
申请号：US12481859
申请日：2009-06-10
申请人： Meng-Tse Weng , Ying-Lieh Chen , Chien-Ru Chen , Chuan-Che Lee
发明人： Meng-Tse Weng , Ying-Lieh Chen , Chien-Ru Chen , Chuan-Che Lee
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G2330/021 , G09G2360/16 , G09G2370/08
摘要： A display, which includes a display panel, a timing controller, and a source driver is provided. The timing controller analyzes gray level distribution of a video data to obtain an analysis result. The source driver is coupled between the display panel and the timing controller for driving the display panel to display a corresponding frame according to a video signal provided by the timing controller, and further the timing controller enables or disables a charge sharing function of the source driver in the display according to the analysis result. As a result, the charge sharing function is enabled optionally during different charge sharing periods, and thus the power consumption and the operation temperature of the source driver could be reduced as compared with the prior art.
摘要翻译：提供了包括显示面板，定时控制器和源驱动器的显示器。时序控制器分析视频数据的灰度分布以获得分析结果。源极驱动器耦合在显示面板和定时控制器之间，用于根据由定时控制器提供的视频信号驱动显示面板显示对应的帧，并且定时控制器启用或禁用源驱动器的电荷共享功能在显示屏上根据分析结果。结果，可以在不同的电荷共享期间选择性地启用电荷共享功能，因此与现有技术相比，能够降低源驱动器的功耗和操作温度。

33. 发明申请

US20100007537A1 HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR WITH SHORTENED SOURCE AND DRAIN 审中-公开
标题翻译：具有短路源和漏极的高压金属氧化物半导体晶体管
公开(公告)号：US20100007537A1
公开(公告)日：2010-01-14
申请号：US12551327
申请日：2009-08-31
申请人： Lin-Kai Bu , Ying-Lieh Chen
发明人： Lin-Kai Bu , Ying-Lieh Chen
IPC分类号： H03M1/66 , H03K17/16
CPC分类号： H01L27/088 , H01L21/823425 , H01L29/7833
摘要： A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate and between the doped regions. Accordingly, the layout area could be substantially reduced.
摘要翻译：提供高电压金属氧化物半导体（HV MOS）晶体管，以在显示装置的源极驱动器中形成解码器，从而基本上节省布局面积。 HV MOS晶体管包括设置在半导体衬底中的具有第一导电类型的两个掺杂区域和在半导体衬底上和掺杂区域之间具有与第一导电类型相反的第二导电类型的栅极区域。因此，可以显着地减少布局面积。

34. 发明授权

US07633482B2 Operational amplifier circuit having digitally controllable output stage 失效
标题翻译：具有数字可控输出级的运算放大器电路
公开(公告)号：US07633482B2
公开(公告)日：2009-12-15
申请号：US11160038
申请日：2005-06-06
申请人： Yu-Jui Chang , Ying-Lieh Chen
发明人： Yu-Jui Chang , Ying-Lieh Chen
IPC分类号： G09G3/36
CPC分类号： H03F3/45475 , G09G3/3685 , H03F2203/45166
摘要： An operational amplifier circuit includes a control stage and an output stage. The control stage includes an analog control stage for generating a first control signal according to an input signal and a digital control stage for generating a second control signal according to the input signal. The output stage includes a sourcing circuitry coupled to the analog control stage and a load for sourcing a first current to the load according to the first control signal, and a sinking circuitry coupled to the digital control stage and the load for sinking a second current from the load according to the second control signal.
摘要翻译：运算放大器电路包括控制级和输出级。控制级包括用于根据输入信号产生第一控制信号的模拟控制级和用于根据输入信号产生第二控制信号的数字控制级。输出级包括耦合到模拟控制级的源电路和用于根据第一控制信号向负载提供第一电流的负载，以及耦合到数字控制级的负载和用于将第二电流从第根据第二控制信号的负载。

35. 发明申请

US20080030452A1 METHOD AND CIRCUIT FOR CONTROLLING THE VOLTAGE POLARITY OF PIXEL STRUCTURE 审中-公开
标题翻译：用于控制像素结构电压极性的方法和电路
公开(公告)号：US20080030452A1
公开(公告)日：2008-02-07
申请号：US11462003
申请日：2006-08-02
申请人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu
发明人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G09G3/36
CPC分类号： G09G3/3614 , G09G3/3655
摘要： In a pixel array, each column of the pixel array is coupled to one of a plurality of first and second channels of a driver. A first and second control signals are generated. Polarities of the first channels are inversed when a logic level of the first control signal changes and polarities of the second channels are inversed when a logic level of the second control signal changes. Only the logic level of one of the first and second control signals changes in response to each transition of scan periods.
摘要翻译：在像素阵列中，像素阵列的每列耦合到驱动器的多个第一和第二通道中的一个。产生第一和第二控制信号。当第二控制信号的逻辑电平改变时，第一通道的极性反转，当第二控制信号的逻辑电平改变时，第二通道的极性反转。只有第一和第二控制信号之一的逻辑电平响应于扫描周期的每个转换而改变。

36. 发明申请

US20070273631A1 Interface circuit for data transmission and method thereof 有权
标题翻译：数据传输接口电路及其方法
公开(公告)号：US20070273631A1
公开(公告)日：2007-11-29
申请号：US11438230
申请日：2006-05-23
申请人： Hsiao-Lan Su , Pen-Hsin Chen , Yu-Jui Chang , Ying-Lieh Chen , Lin-Kai Bu
发明人： Hsiao-Lan Su , Pen-Hsin Chen , Yu-Jui Chang , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G09G3/36
CPC分类号： G09G3/3611 , G09G3/3688 , G09G2330/06
摘要： An interface circuit for data transmission and the method thereof is described. The interface circuit includes a transmitter providing data through first data signals during the data periods corresponding to rising and falling edges of a clock signal, a transition detection unit selectively asserting a detection signal in response to the number of the first data signals having transitions between every two adjacent data periods, a transition reduction unit generating second data signals by outputting the inverted and non-inverted first data signals respectively when the detection signal is asserted and de-asserted, and a receiver restoring the data from the second data signals and the detection signal.
摘要翻译：描述了用于数据传输的接口电路及其方法。接口电路包括：在与时钟信号的上升沿和下降沿相对应的数据周期期间通过第一数据信号提供数据的发射器，转换检测单元响应于第一数据信号的数量响应于每个两个相邻数据周期，转换缩减单元，当检测信号被断言和解除断言时分别输出反相和非反相第一数据信号，并且接收机从第二数据信号恢复数据和检测信号。

37. 发明授权

US07286011B2 Operational amplifier circuit having adjustable bias current 有权
标题翻译：具有可调偏置电流的运算放大器电路
公开(公告)号：US07286011B2
公开(公告)日：2007-10-23
申请号：US11160039
申请日：2005-06-07
申请人： Yu-Jui Chang , Ying-Lieh Chen
发明人： Yu-Jui Chang , Ying-Lieh Chen
IPC分类号： H03F1/14
CPC分类号： H03F3/45475 , H03F1/0261 , H03F3/72 , H03F2203/45136 , H03F2203/7203
摘要： An operational amplifier circuit includes an operational amplifier, a bias current provider, and a control circuitry. The operational amplifier drives a load according to an input signal. The bias current provider is coupled to the operational amplifier and provides a bias current to the operational amplifier. The control circuitry is coupled to the bias current provider and controls the bias current provider to adjust the bias current according to an operating status of the operational amplifier circuit.
摘要翻译：运算放大器电路包括运算放大器，偏置电流提供器和控制电路。运算放大器根据输入信号驱动负载。偏置电流提供器耦合到运算放大器，并向运算放大器提供偏置电流。控制电路耦合到偏置电流提供器，并根据运算放大器电路的运行状态控制偏置电流提供器来调整偏置电流。

38. 发明授权

US07271661B2 Operation amplifier circuit having digital driving circuitry and analog driving circuitry 有权
标题翻译：具有数字驱动电路和模拟驱动电路的运算放大器电路
公开(公告)号：US07271661B2
公开(公告)日：2007-09-18
申请号：US10908989
申请日：2005-06-03
申请人： Yu-Jui Chang , Ying-Lieh Chen
发明人： Yu-Jui Chang , Ying-Lieh Chen
IPC分类号： H03F3/68 , H03F3/217
CPC分类号： H03F3/217 , H03F3/211
摘要： An operational amplifier circuit includes an analog driving circuitry and a digital driving circuitry. The analog driving circuitry is coupled to a load and drives the load according to an input signal. The digital driving circuitry includes a code comparator, a sourcing unit, and a sinking unit. The code comparator compares a reference code with codes corresponding to the input signal and generates a first control signal and a second control signal accordingly. The sourcing unit is coupled to the code comparator and the load, and sources a first current to the load according to the first control signal. The sinking unit is coupled to the code comparator and the load, and sinks a second current from the load according to the second control signal.
摘要翻译：运算放大器电路包括模拟驱动电路和数字驱动电路。模拟驱动电路耦合到负载并根据输入信号驱动负载。数字驱动电路包括代码比较器，源单元和下沉单元。代码比较器将参考代码与对应于输入信号的代码进行比较，并相应地产生第一控制信号和第二控制信号。源单元耦合到代码比较器和负载，并根据第一控制信号向负载发送第一电流。吸收单元耦合到代码比较器和负载，并根据第二控制信号从负载吸收第二电流。

39. 发明授权

US07161517B1 Digital-to-analog converter 有权
标题翻译：数模转换器
公开(公告)号：US07161517B1
公开(公告)日：2007-01-09
申请号：US11168334
申请日：2005-06-29
申请人： Chen-Song Yen , Tsung-Yu Wu , Ying-Lieh Chen , Lin-Kai Bu
发明人： Chen-Song Yen , Tsung-Yu Wu , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： H03M1/66
CPC分类号： H03M1/68 , H03M1/76
摘要： A DAC has an N-bit R-string DAC section and an (M-N)-bit interpolation DAC section. The N-bit R-string DAC section has a plurality of resistors and a 2-of-N selector. The resistors are electrically connected in series to provide a plurality of voltage levels. The 2-of-N selector is coupled to the series-connected resistors, and is arranged to select two neighboring voltage levels according to an N-bit MSB subword. The (M-N)-bit interpolation DAC section is coupled to the N-bit R-string DAC section, and is arranged to interpolate an analog output signal from the two neighboring voltage levels according to an (M-N)-bit LSB subword.
摘要翻译： DAC具有N位R串DAC部分和（M-N）位插值DAC部分。 N位R串DAC部分具有多个电阻和2位N选择器。电阻器串联电连接以提供多个电压电平。 2位N选择器耦合到串联电阻器，并且被布置为根据N位MSB子字选择两个相邻的电压电平。（M-N）位插值DAC部分耦合到N位R串DAC部分，并且被配置为根据（M-N）位LSB子字来插入来自两个相邻电压电平的模拟输出信号。

40. 发明申请

US20060108616A1 High-voltage metal-oxide-semiconductor transistor 审中-公开
标题翻译：高压金属氧化物半导体晶体管
公开(公告)号：US20060108616A1
公开(公告)日：2006-05-25
申请号：US10992784
申请日：2004-11-22
申请人： Lin-Kai Bu , Ying-Lieh Chen
发明人： Lin-Kai Bu , Ying-Lieh Chen
IPC分类号： H01L29/94
CPC分类号： H01L27/088 , H01L21/823425 , H01L29/7833
摘要： A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate and between the doped regions. Accordingly, the layout area could be substantially reduced.
摘要翻译：提供高电压金属氧化物半导体（HV MOS）晶体管，以在显示装置的源极驱动器中形成解码器，从而基本上节省了布局面积。 HV MOS晶体管包括设置在半导体衬底中的具有第一导电类型的两个掺杂区域和在半导体衬底上和掺杂区域之间具有与第一导电类型相反的第二导电类型的栅极区域。因此，可以显着地减少布局面积。

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