专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08422200B2 Conductive structure having an embedded electrode, and solid capacitor having an embedded electrode and method of making the same 有权
标题翻译：具有嵌入电极的导电结构和具有嵌入电极的固体电容器及其制造方法
公开(公告)号：US08422200B2
公开(公告)日：2013-04-16
申请号：US13115964
申请日：2011-05-25
申请人： Wei-Chih Lee , Ming-Tsung Chen
发明人： Wei-Chih Lee , Ming-Tsung Chen
IPC分类号： H01G9/00
CPC分类号： H01G9/012 , H01G9/052 , H01G9/15 , Y10T29/435
摘要： A solid capacitor having an embedded electrode includes a substrate unit, a first conductive unit, a second conductive unit, a first insulative unit, a third conductive unit, a second insulative unit, and an end electrode unit. The substrate unit includes a substrate body and a conductive body embedded into the substrate body. The substrate body has a lateral opening and a plurality of top openings, and the conductive body has a lateral conductive area exposed from the lateral opening and a plurality of top conductive areas respectively exposed from the top openings. The first conductive unit includes a plurality of first conductive layers respectively covering the top conductive areas. The second conductive unit includes a second conductive layer covering the first conductive layers. The porosity rate of the second conductive layer is larger than that of each first conductive layer.
摘要翻译：具有嵌入电极的固体电容器包括基板单元，第一导电单元，第二导电单元，第一绝缘单元，第三导电单元，第二绝缘单元和端电极单元。基板单元包括基板主体和嵌入基板主体中的导电体。基板主体具有侧向开口和多个顶部开口，并且导电体具有从侧向开口暴露的横向导电区域和分别从顶部开口露出的多个顶部导电区域。第一导电单元包括分别覆盖顶部导电区域的多个第一导电层。第二导电单元包括覆盖第一导电层的第二导电层。第二导电层的孔隙率大于每个第一导电层的孔隙率。

32. 发明申请

US20110143511A1 Method of fabricating n-channel metal-oxide semiconductor transistor 有权
标题翻译：制造n沟道金属氧化物半导体晶体管的方法
公开(公告)号：US20110143511A1
公开(公告)日：2011-06-16
申请号：US12636788
申请日：2009-12-14
申请人： I-Chang Wang , Ling-Chun Chou , Ming-Tsung Chen
发明人： I-Chang Wang , Ling-Chun Chou , Ming-Tsung Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L29/665 , H01L29/66628
摘要： A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer.
摘要翻译：一种制造NMOS晶体管的方法，其中在执行自对准硅化处理之前形成外延硅层，然后形成自对准硅化物处理所需的镍层，然后进行快速热处理，以使镍层，以在外延硅层下与外延硅层和硅衬底反应以形成硅化镍层。

33. 发明授权

US07384853B2 Method of performing salicide processes on MOS transistors 有权
标题翻译：在MOS晶体管上执行自对准硅化物处理的方法
公开(公告)号：US07384853B2
公开(公告)日：2008-06-10
申请号：US11161990
申请日：2005-08-25
申请人： Ming-Tsung Chen , Chang-Chi Huang , Po-Chao Tsao
发明人： Ming-Tsung Chen , Chang-Chi Huang , Po-Chao Tsao
IPC分类号： H01L21/331
CPC分类号： H01L21/28518 , H01L21/26506 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7834
摘要： A method of performing salicide processes on a MOS transistor, wherein the MOS transistor comprises a gate structure and a source/drain region, the method comprising: performing a selective growth process to form a silicon layer on the top of the gate and the source/drain region; performing an ion implantation process to form a retarded interface layer between the silicon layer and the gate and source/drain region; forming a metal layer on the silicon layer; and reacting the metal layer with the silicon layer for forming a silicide layer.
摘要翻译：一种在MOS晶体管上执行自对准硅化物工艺的方法，其中所述MOS晶体管包括栅极结构和源极/漏极区域，所述方法包括：执行选择性生长工艺以在所述栅极的顶部上形成硅层，并且所述源/ 漏区; 执行离子注入工艺以在硅层和栅极和源极/漏极区之间形成延迟界面层; 在所述硅层上形成金属层; 并使金属层与用于形成硅化物层的硅层反应。

34. 发明申请

US20070166936A1 PRE-AMORPHIZATION IMPLANTATION PROCESS AND SALICIDE PROCESS 审中-公开
标题翻译：预处理植入过程和杀真菌过程
公开(公告)号：US20070166936A1
公开(公告)日：2007-07-19
申请号：US11307008
申请日：2006-01-19
申请人： Po-Chao Tsao , Yi-Yiing Chiang , Chang-Chi Huang , Hsin-Hui Hsu , Ming-Tsung Chen , Chien-Ting Lin
发明人： Po-Chao Tsao , Yi-Yiing Chiang , Chang-Chi Huang , Hsin-Hui Hsu , Ming-Tsung Chen , Chien-Ting Lin
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/665 , H01L29/6659
摘要： A salicide process is described, wherein a substrate with an NMOS transistor and a PMOS transistor thereon is provided. A mask layer is formed over the substrate covering the PMOS transistor but exposing the NMOS transistor, and then a pre-amorphization implantation (PAI) step is conducted to the substrate using the mask layer as a mask. After the mask layer is removed, a salicide layer is formed on the NMOS transistor and the PMOS transistor.
摘要翻译：描述了自对准硅化物工艺，其中提供了具有NMOS晶体管和PMOS晶体管的衬底。在覆盖PMOS晶体管的衬底上形成掩模层，但暴露NMOS晶体管，然后使用掩模层作为掩模将前非晶化注入（PAI）步骤传导到衬底。在去除掩模层之后，在NMOS晶体管和PMOS晶体管上形成自对准硅层。

35. 发明申请

US20070082489A1 METHOD OF FABRICATING OPENINGS AND CONTACT HOLES 有权
标题翻译：制作开口和接触孔的方法
公开(公告)号：US20070082489A1
公开(公告)日：2007-04-12
申请号：US11163149
申请日：2005-10-06
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the etch stop layer. The dielectric thin film disposed on the dielectric layer and the etch stop layer is then removed.
摘要翻译：提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的衬底。然后将电介质层图案化以形成露出蚀刻停止层的多个开口。随后形成介电薄膜以覆盖电介质层，开口的侧壁和蚀刻停止层。然后去除设置在电介质层和蚀刻停止层上的电介质薄膜。

36. 发明申请

US20070054481A1 SEMICONDUCTOR DEVICE HAVING NICKEL SILICIDE AND METHOD OF FABRICATING NICKEL SILICIDE 有权
标题翻译：具有尼龙硅胶的半导体器件及其制造方法
公开(公告)号：US20070054481A1
公开(公告)日：2007-03-08
申请号：US11162360
申请日：2005-09-08
申请人： Yi-Wei Chen , Chao-Ching Hsieh , Yi-Yiing Chiang , Tzung-Yu Hung , Yu-Lan Chang , Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
发明人： Yi-Wei Chen , Chao-Ching Hsieh , Yi-Yiing Chiang , Tzung-Yu Hung , Yu-Lan Chang , Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
IPC分类号： H01L21/28
CPC分类号： H01L29/665 , H01L21/324 , H01L29/4933
摘要： A semiconductor device having nickel suicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed thereunder. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.
摘要翻译：一种具有镍硅化物的半导体器件和一种制造硅化镍的方法。提供具有多个掺杂区域的半导体衬底。接着，在半导体基板上形成镍层，进行第一快速热处理（RTP），使镍层与配置在其上的掺杂区域反应。此后，除去未反应的镍层，进行第二快速热处理以形成具有硅化镍的半导体器件。第二快速热处理是工艺温度在400和600℃之间的尖峰退火工艺。

37. 发明授权

US11408782B2 Indoor temperature control system 有权
公开(公告)号：US11408782B2
公开(公告)日：2022-08-09
申请号：US16594778
申请日：2019-10-07
申请人： Ming-Tsung Chen
发明人： Ming-Tsung Chen
IPC分类号： G01K17/08 , F24F11/64 , F24F11/76 , F24F11/52 , F24F110/10
摘要： An indoor temperature control system includes a server, a first temperature sensor, a second temperature sensor, and a third temperature sensor. The server obtains a first heat adjustment amount according to a first temperature value of the first temperature sensor. The server obtains a second heat adjustment amount according to a second temperature value of the second temperature sensor. The server obtains a predetermined amount of heat of a predetermined region according to a third temperature value of the third temperature sensor. The server obtains a heat flow simulation diagram according to the first heat adjustment amount, the second heat adjustment amount, and the predetermined amount of heat. The server determines an operating time of an air conditioning device based on a target temperature, the second temperature value, and the heat flow simulation diagram.

38. 发明授权

US11137266B2 Electric meter monitoring device and electric power monitoring system 有权
公开(公告)号：US11137266B2
公开(公告)日：2021-10-05
申请号：US16198813
申请日：2018-11-22
申请人： Ming-Tsung Chen
发明人： Ming-Tsung Chen
IPC分类号： G01D4/00 , G01R19/25
摘要： An electric meter monitoring device and an electric power monitoring system are provided. An image capturing module is disposed at a side opposite to an electric power consumption display module of an electric meter to capture an electric power consumption image of the electric power consumption display module. A clamp meter module clamps on at least one electric wire to detect a value of a current flowing through the at least one electric wire. A temperature humidity meter module detects a temperature value and a humidity value around the electric meter. A control module transmits an electric power consumption value, a current value, the temperature value and the humidity value to a server through a communication module.

39. 发明授权

US10826995B2 Electric device monitoring system and electric device monitoring method 有权
公开(公告)号：US10826995B2
公开(公告)日：2020-11-03
申请号：US16236214
申请日：2018-12-28
申请人： Ming-Tsung Chen
发明人： Ming-Tsung Chen
IPC分类号： G01R31/14 , G01R31/28 , H04L29/08 , H04L12/28 , H04L29/06 , H04Q9/00 , G01R31/50 , G01R31/52 , G01R31/58 , G01R31/34 , G01R31/54 , G01R31/66
摘要： An electronic device monitoring system includes a server, a first electronic device, and a first power feature identifying device. The first electronic device is electrically connected to a grid. A first voltage and a first current are variable. The first power feature identifying device communicates with the server by a first communication protocol. The first power feature identifying device is disposed between the first electronic device and the grid. The first power feature identifying device extracts a plurality of voltage-time features, a plurality of current-time features, and a plurality of voltage-current features of the first electronic device in a first predetermined time, and the first power feature identifying device transmits those features to the server to generate a first power profile based thereon. The server monitors whether the first electronic device is in normal operation based on the first power profile.

40. 发明授权

US09136348B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09136348B2
公开(公告)日：2015-09-15
申请号：US13417337
申请日：2012-03-12
申请人： Ming-Te Wei , Shin-Chuan Huang , Yu-Hsiang Hung , Po-Chao Tsao , Chia-Jui Liang , Ming-Tsung Chen , Chia-Wen Liang
发明人： Ming-Te Wei , Shin-Chuan Huang , Yu-Hsiang Hung , Po-Chao Tsao , Chia-Jui Liang , Ming-Tsung Chen , Chia-Wen Liang
IPC分类号： H01L29/66 , H01L29/78 , H01L29/165
CPC分类号： H01L29/66492 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.
摘要翻译：半导体结构包括设置在基板上并具有外部间隔件的栅极结构，设置在基板中并与栅极结构相邻的凹槽，填充凹部的掺杂的外延材料，包括未掺杂的外延材料的盖层，所述掺杂的外延材料是设置在所述覆盖层下方并且夹在所述掺杂的外延材料和所述覆盖层之间的轻掺杂漏极，以及设置在所述覆盖层上并覆盖所述掺杂外延材料以与所述外部间隔物一起覆盖所述覆盖层的硅化物而不直接接触轻掺杂的漏极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式