专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20050188292A1 Method and apparatus for encoding special uncorrectable errors in an error correction code 失效
标题翻译：用于在纠错码中编码特殊不可校正错误的方法和装置
公开(公告)号：US20050188292A1
公开(公告)日：2005-08-25
申请号：US10744833
申请日：2003-12-23
申请人： Chin-Long Chen
发明人： Chin-Long Chen
IPC分类号： G11C29/00 , G11C29/42
CPC分类号： H03M13/13 , G11C29/42
摘要： An error correction code for encoding the presence of a special uncorrectable error as well as its type. In the encoder, modification logic modifies the regular data symbols to indicate the type of special uncorrectable error. The encoder appends to the regular data symbols a special uncorrectable error symbol indicating the presence of a special uncorrectable error to form an extended data word, which is encoded to generate a code word. In the decoder, a syndrome generator generates a syndrome vector using an assumed value for the special uncorrectable error symbol indicating the absence of a special uncorrectable error, while a syndrome decoder determines the presence of the special uncorrectable error by determining the presence of an error in the assumed value of the special uncorrectable error symbol. By so using its error detection logic, the decoder makes it unnecessary to actually store or transmit the special uncorrectable error symbol.
摘要翻译：用于编码存在特殊不可校正错误及其类型的纠错码。在编码器中，修改逻辑修改常规数据符号以指示特殊不可校正错误的类型。编码器将常规数据符号附加到指示存在特殊的不可校正错误的特殊不可校正错误符号，以形成扩展数据字，该扩展数据字被编码以生成代码字。在解码器中，校正子发生器使用指示不存在特殊不可校正错误的特殊不可校正错误符号的假设值来生成校正子向量，而校正子解码器通过确定存在错误来确定特殊的不可校正错误特殊不可校正错误符号的假定值。通过使用其错误检测逻辑，解码器不需要实际存储或发送特殊的不可校正错误符号。

32. 发明申请

US20050118768A1 METHOD OF FORMING HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR 有权
标题翻译：形成高压金属氧化物半导体晶体管的方法
公开(公告)号：US20050118768A1
公开(公告)日：2005-06-02
申请号：US10707217
申请日：2003-11-27
申请人： Chin-Long Chen
发明人： Chin-Long Chen
IPC分类号： H01L21/266 , H01L21/336 , H01L29/78 , H01L21/8238 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/266 , H01L29/7833
摘要： A polysilicon layer and a first patterned photoresist layer are formed on a substrate. An ultraviolet curing process is performed to cure the first patterned photoresist layer. Then, a gate structure is formed by using the first patterned photoresist layer as a hard mask. A second patterned photoresist layer is formed on the substrate. The second patterned photoresist layer, the cured remaining first patterned photoresist layer and the gate form two openings alongside the gate structure. Finally, via the openings, two consecutive ion implantation processes are performed to form a double diffuse drain (DDD) structure.
摘要翻译：在基板上形成多晶硅层和第一图案化光致抗蚀剂层。执行紫外线固化工艺以固化第一图案化光致抗蚀剂层。然后，通过使用第一图案化光致抗蚀剂层作为硬掩模形成栅极结构。在基板上形成第二图案化光致抗蚀剂层。第二图案化光致抗蚀剂层，固化的剩余的第一图案化光致抗蚀剂层和栅极沿着栅极结构形成两个开口。最后，通过开口，执行两个连续的离子注入工艺以形成双扩散漏极（DDD）结构。

33. 发明授权

US06675341B1 Extended error correction for SEC-DED codes with package error detection ability 失效
标题翻译：具有封装错误检测能力的SEC-DED代码的扩展错误校正
公开(公告)号：US06675341B1
公开(公告)日：2004-01-06
申请号：US09442435
申请日：1999-11-17
申请人： Chin-Long Chen , Douglas C. Bossen
发明人： Chin-Long Chen , Douglas C. Bossen
IPC分类号： H03M1300
CPC分类号： H03M13/19 , G06F11/1028 , H03M13/11
摘要： An apparatus and method is provided for correcting data words resulting from a package fail within a memory array in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure. The invention correcting exploits single error correcting (SEC)-and double error detecting (DED) codes, requiring no additional check bits, which give a syndrome when the data word has suffered an error coming from at least one error in a package.
摘要翻译：提供了一种装置和方法，用于在编码数据被分成多个b位的多位数据包的存储器阵列中校正由封装故障引起的数据字。编码数据包括具有r个纠错码位和n-r个数据位的n位字。本发明能够校正已遭受至少一次硬故障的一个包装。本发明的校正利用单纠错（SEC）和双重错误检测（DED）代码，不需要额外的校验位，当数据字遭受到来自封装中的至少一个错误的错误时，该错误校正位发生错误。

34. 发明授权

US06539513B1 Dual functioning symbol error correction code 失效
标题翻译：双功能符号纠错码
公开(公告)号：US06539513B1
公开(公告)日：2003-03-25
申请号：US09417948
申请日：1999-10-13
申请人： Chin-Long Chen
发明人： Chin-Long Chen
IPC分类号： H03M1300
CPC分类号： G06F11/1008 , H03M13/6575
摘要： A method for constructing a single ECC that incorporates two codes into one is presented. This single ECC configuration can be applied to a memory configured in 2-bit-per-chip or 4-bit-per-chip. A mode bit M is used to indicate one of the two memory configurations.
摘要翻译：提出了一种将两个代码并入到一个中的单个ECC的构造方法。这种单一的ECC配置可以应用于以2位/位或每位芯片配置的存储器。模式位M用于指示两个存储器配置之一。

35. 发明授权

US06386456B1 Memory card identification system 失效
标题翻译：存储卡识别系统
公开(公告)号：US06386456B1
公开(公告)日：2002-05-14
申请号：US09326233
申请日：1999-06-04
申请人： Chin-Long Chen , Charles D. Holtz , Giacomo V. Ingenio , William W. Shen
发明人： Chin-Long Chen , Charles D. Holtz , Giacomo V. Ingenio , William W. Shen
IPC分类号： G06K1900
CPC分类号： H01L23/544 , H01L23/5258 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002 , H01L2924/00
摘要： In a memory card, identification numbers identifying the memory card are permanently stored in fuse blown registers formed in each of two redrive chips, which function to read out data from memory chips of the memory card and store data in the memory chips of the memory card. Each identification number separately provides a unique identification of the memory card. The identification numbers are each stored with an error correction code by which single bit errors en the identification numbers can be corrected and the occurrence of multiple bit errors in the identification numbers can be detected. Both identification numbers, if valid, are used to identify the memory card and both of the identification numbers, if valid, are stored in association with memory quality events occurring on the memory card, so as to provide a redundant identification of the memory card on which the memory quality events occurred.
摘要翻译：在存储卡中，识别存储卡的标识号永久存储在形成于两个重新驱动芯片中的每一个中的熔丝烧写寄存器中，其功能是从存储卡的存储器芯片读出数据并将数据存储在存储卡的存储器芯片中。每个标识号分别提供存储卡的唯一标识。识别号码各自存储有纠错码，通过该纠错码可以校正识别号码中的单个比特错误，并且可以检测识别号码中的多个比特错误的发生。两个识别号码（如果有效）用于识别存储卡，并且如果存在与存储卡上存在的存储器质量事件相关联地存储两个标识号码（如果有效），以便在存储卡上提供存储卡的冗余标识内存质量事件发生。

36. 发明授权

US5774481A Reduced gate error detection and correction circuit 失效
标题翻译：减少门误差检测和校正电路
公开(公告)号：US5774481A
公开(公告)日：1998-06-30
申请号：US414064
申请日：1995-03-31
申请人： Patrick James Meaney , Chin-Long Chen
发明人： Patrick James Meaney , Chin-Long Chen
IPC分类号： G06F11/10 , H03M13/13 , H03M13/00
CPC分类号： G06F11/1012 , H03M13/13
摘要： Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit position. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.
摘要翻译：错误检测和校正电路，经过优化，可减少校正单个错误所需的时间并检测是否存在不可校正的错误，使用优化的H-Matrix并提供减少的逻辑电路。可纠正的误差综合征被定义为包括奇数个，并且当检测到偶数个错误时，不可校正错误检测电路产生不可校正错误指示。可校正错误综合征被定义为在一组相应位位置中的每一个中具有预定义的1和0的组合，以及在其它位位置中具有不同的1和0的组合。仅包括零的错误综合征被指定为无错误状态的指示。提供逻辑电路，其实现具有减少的逻辑门集合的错误检测和校正电路。

37. 发明授权

US5768294A Memory implemented error detection and correction code capable of detecting errors in fetching data from a wrong address 失效
标题翻译：存储器实现的错误检测和纠错码能够检测从错误地址获取数据的错误
公开(公告)号：US5768294A
公开(公告)日：1998-06-16
申请号：US570448
申请日：1995-12-11
申请人： Chin-Long Chen , Mu-Yue Hsiao , Walter Heinrich Lipponer , William Wu Shen
发明人： Chin-Long Chen , Mu-Yue Hsiao , Walter Heinrich Lipponer , William Wu Shen
IPC分类号： G06F11/10 , H03M13/03 , H03M13/00
CPC分类号： G06F11/1016 , G06F11/1028 , H03M13/03
摘要： An apparatus and method is discussed using a parity check matrix in order to acheive correction and detection of errors particularly pertaining to detection data fetched from a wrong address. The code structure enhances utilization of chip reliability by encoding and decoding digital signals through the utilization of a parity check matrix and parity bits generated from system address bits of a computer system with k symbols and b bits per symbol.
摘要翻译：使用奇偶校验矩阵来讨论使用奇偶校验矩阵的装置和方法，以便对来自错误地址的检测数据特别有关的错误进行矫正和检测。代码结构通过利用奇偶校验矩阵和由每个符号k个符号和b位的计算机系统的系统地址位产生的奇偶校验位对数字信号进行编码和解码来提高芯片可靠性的利用率。

38. 发明授权

US5754562A Method and apparatus for encoding certain double-error correcting and triple-error detecting codes 失效
公开(公告)号：US5754562A
公开(公告)日：1998-05-19
申请号：US705471
申请日：1996-08-29
申请人： Chin-Long Chen
发明人： Chin-Long Chen
IPC分类号： H03M13/15 , H03M13/00
CPC分类号： H03M13/151
摘要： BCH error correcting code principles are employed in conjunction with normal basis representation of field elements to provide apparatus and method for encoding and decoding binary electrical signals in a way which ensures the ability to correct all double-bit errors and to detect all triple-bit errors. Both the encoder and decoder are designed in a fashion which permits modular implementation so as to make the circuits more compact and easier to layout.

39. 发明授权

US5751745A Memory implemented error detection and correction code with address parity bits 失效
标题翻译：存储器实现了具有地址奇偶校验位的错误检测和校正码
公开(公告)号：US5751745A
公开(公告)日：1998-05-12
申请号：US824098
申请日：1997-03-25
申请人： Chin-Long Chen , Mu-Yue Hsiao , Walter Heinrich Lipponer , William Wu Shen
发明人： Chin-Long Chen , Mu-Yue Hsiao , Walter Heinrich Lipponer , William Wu Shen
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1016 , G06F11/1028
摘要： A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.
摘要翻译：一种用于通过使用一串接收到的进入系统地址位来执行数字信号错误检测的方法和装置。输入地址位根据它们是否包含高值“1”或低值“0”分成组。然后从每个组生成至少一个地址奇偶校验位，并用于检查接收到的数据的完整性。

40. 发明授权

US5682394A Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature 失效
标题翻译：容错计算机存储器系统和采用双级错误校正和检测功能的组件
公开(公告)号：US5682394A
公开(公告)日：1997-10-28
申请号：US012186
申请日：1993-02-02
申请人： Robert Martin Blake , Douglas Craig Bossen , Chin-Long Chen , John Atkinson Fifield , Howard Leo Kalter
发明人： Robert Martin Blake , Douglas Craig Bossen , Chin-Long Chen , John Atkinson Fifield , Howard Leo Kalter
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which is tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
摘要翻译：在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级错误校正能力，并且每个都与系统级错误校正功能相关联，通过提供用于禁用单元级错误校正的机制来增强存储器的可靠性能力，例如，响应于在一个存储器单元中发生不可校正的错误。这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式