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31. 发明申请

US20100257498A1 INCREMENTAL TIMING OPTIMIZATION AND PLACEMENT 有权
标题翻译：增量时序优化和放置
公开(公告)号：US20100257498A1
公开(公告)日：2010-10-07
申请号：US12416754
申请日：2009-04-01
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.
摘要翻译：公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。响应于合法化，EDA系统递增地优化多个路径的时间延迟。

32. 发明授权

US08793636B2 Placement of structured nets 有权
标题翻译：结构化网络的布置
公开(公告)号：US08793636B2
公开(公告)日：2014-07-29
申请号：US13086428
申请日：2011-04-14
申请人： Charles J. Alpert , Myung-Chul Kim , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Myung-Chul Kim , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells.
摘要翻译：提供了用于在半导体器件的设计中执行电池放置的机构。生成半导体器件的初始设计，初始设计包括单元的第一放置。确定与细胞相关联的放置的优选方向。优选的方向是细胞扩散优选的方向。基于与单元相关联的放置的优选方向，通过修改单元的第一放置以产生与第一放置单元不同的单元的第二放置来生成半导体器件的第二设计。

33. 发明授权

US08347249B2 Incremental timing optimization and placement 有权
标题翻译：增量时序优化和放置
公开(公告)号：US08347249B2
公开(公告)日：2013-01-01
申请号：US12416754
申请日：2009-04-01
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
IPC分类号： G06F9/455
CPC分类号： G06F17/505
摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.
摘要翻译：公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。响应于合法化，EDA系统递增地优化多个路径的时间延迟。

34. 发明授权

US07707530B2 Incremental timing-driven, physical-synthesis using discrete optimization 有权
标题翻译：使用离散优化的增量式时序驱动，物理合成
公开(公告)号：US07707530B2
公开(公告)日：2010-04-27
申请号：US11941105
申请日：2007-11-16
申请人： Charles J. Alpert , Zhuo Li , Michael D. Moffitt , David A. Papa
发明人： Charles J. Alpert , Zhuo Li , Michael D. Moffitt , David A. Papa
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , G06F2217/84
摘要： A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Path Smoothing utility identifies one or more movable gates based on at least one selection criteria. A set of legalized candidate locations corresponding to one or more identified movable gates is generated. A disjunctive timing graph based on the generated set of legalized candidate locations is then generated. An optimal location of one or more movable gate(s) is determined using a recursive branch-and-bound search and stored in the computing device.
摘要翻译：一种用于优化物理合成流中子电路的逻辑门的布置的方法，数据处理系统和计算机程序产品。路径平滑实用程序基于至少一个选择标准识别一个或多个可移动门。生成与一个或多个识别的可移动门对应的一组合法化候选位置。然后生成基于生成的合法化候选位置集合的分离时序图。一个或多个可移动门的最佳位置使用递归分支搜索并被存储在计算设备中来确定。

35. 发明授权

US08347257B2 Detailed routability by cell placement 有权
标题翻译：细胞放置的详细路线
公开(公告)号：US08347257B2
公开(公告)日：2013-01-01
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

36. 发明申请

US20110302544A1 POST-PLACEMENT CELL SHIFTING 失效
标题翻译：后置放电细胞移位
公开(公告)号：US20110302544A1
公开(公告)日：2011-12-08
申请号：US12796550
申请日：2010-06-08
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块。扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。扩张器也可能使这些细胞膨胀并合法化。

37. 发明授权

US08589848B2 Datapath placement using tiered assignment 有权
标题翻译： Datapath放置使用分层分配
公开(公告)号：US08589848B2
公开(公告)日：2013-11-19
申请号：US13451382
申请日：2012-04-19
申请人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information.
摘要翻译：数据路径布局定义了单元格集群的布局集合的层次，将单元格分配给由数据路径宽度约束的层，然后在每个层中排序单元格。使用基于机器学习的数据路径提取来识别群集。数据路径宽度通过计算群集中的单元格的边界框的大小来确定。使用从集群的输入单元开始的宽度优先搜索来标识放置集。最初使用逻辑深度分配定义层次。可以通过从下一较高层拉动单元以填充空位或通过将多余单元推入下一较高层来将单元分配给层。根据线长成本函数，使用贪心小区分配在每个层中对单元进行排序。数据路径放置可以是迭代过程的一部分，其基于计算的拥塞信息将扩展约束应用于集群。

38. 发明申请

US20130283225A1 DATAPATH PLACEMENT USING TIERED ASSIGNMENT 有权
标题翻译：使用方式分配的DATAPATH放置
公开(公告)号：US20130283225A1
公开(公告)日：2013-10-24
申请号：US13451382
申请日：2012-04-19
申请人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information.
摘要翻译：数据路径布局定义了单元格集群的布局集合的层次，将单元格分配给由数据路径宽度约束的层，然后在每个层中排序单元格。使用基于机器学习的数据路径提取来识别群集。数据路径宽度通过计算群集中的单元格的边界框的大小来确定。使用从集群的输入单元开始的宽度优先搜索来标识放置集。最初使用逻辑深度分配定义层次。可以通过从下一较高层拉动单元以填充空位或通过将多余单元推入下一较高层来将单元分配给层。根据线长成本函数，使用贪心小区分配在每个层中对单元进行排序。数据路径放置可以是迭代过程的一部分，其基于计算的拥塞信息将扩展约束应用于集群。

39. 发明申请

US20130086537A1 Design Routability Using Multiplexer Structures 失效
标题翻译：使用多路复用器结构设计路由
公开(公告)号：US20130086537A1
公开(公告)日：2013-04-04
申请号：US13248119
申请日：2011-09-29
申请人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
发明人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation.
摘要翻译：提供用于产生集成电路器件的逻辑设计的机构。接收集成电路设备的初始逻辑设计表示，并且识别初始逻辑设计表示的一个或多个区域，其中一个或多个区域中的逻辑元件可被一个或多个多路复用器树结构替代。初始逻辑设计表示的一个或多个区域中的逻辑元件被多路复用器树结构替代以生成修改的逻辑设计表示。经修改的逻辑设计表示被输出到物理合成系统，以基于经修改的逻辑设计表示来生成集成电路器件的物理布局。

40. 发明申请

US20120266124A1 Placement of Structured Nets 有权
标题翻译：结构网的布置
公开(公告)号：US20120266124A1
公开(公告)日：2012-10-18
申请号：US13086428
申请日：2011-04-14
申请人： Charles J. Alpert , Myung-Chul Kim , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Myung-Chul Kim , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells.
摘要翻译：提供了用于在半导体器件的设计中执行电池放置的机构。生成半导体器件的初始设计，初始设计包括单元的第一放置。确定与细胞相关联的放置的优选方向。优选的方向是细胞扩散优选的方向。基于与单元相关联的放置的优选方向，通过修改单元的第一放置以产生与第一放置单元不同的单元的第二放置来生成半导体器件的第二设计。

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