专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07934074B2 Flash module with plane-interleaved sequential writes to restricted-write flash chips 有权
标题翻译：闪存模块，具有平面交错顺序写入限制写入闪存芯片
公开(公告)号：US07934074B2
公开(公告)日：2011-04-26
申请号：US11871011
申请日：2007-10-11
申请人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
发明人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F12/0607 , G06F2212/7201 , G06F2212/7208 , G11C11/5621 , G11C16/0408
摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.
摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。

32. 发明授权

US07865630B2 Single-chip multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage 有权
标题翻译：单芯片多媒体卡/安全数字（MMC / SD）控制器从集成闪存读取上电启动代码，用于用户存储
公开(公告)号：US07865630B2
公开(公告)日：2011-01-04
申请号：US12426378
申请日：2009-04-20
申请人： I-Kang Frank Yu , Abraham C. Ma , Charles C. Lee
发明人： I-Kang Frank Yu , Abraham C. Ma , Charles C. Lee
IPC分类号： G06F3/00 , G06F13/28 , G06F13/12 , G06F9/00
CPC分类号： G06F13/28 , Y02D10/14
摘要： A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.
摘要翻译：多媒体卡/安全数字（MMC / SD）单芯片闪存设备包含一个MMC / SD闪存微控制器和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。来自主机MMC / SD总线的MMC / SD事务由MMC / SD闪存微控制器上的总线收发器读取。响应于MMC / SD事务中的命令，激活在MMC / SD闪存单片机中的CPU上执行的各种例程。 MMC / SD闪存单片机中的闪存控制器将数据从总线收发器传输到闪存大容量存储块以进行存储。不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

33. 发明授权

US07707321B2 Chained DMA for low-power extended USB flash device without polling 失效
标题翻译：用于低功耗扩展USB闪存设备的链接DMA，无轮询
公开(公告)号：US07707321B2
公开(公告)日：2010-04-27
申请号：US11928124
申请日：2007-10-30
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
IPC分类号： G06F3/00 , G06F13/38
CPC分类号： G06F13/28 , Y02D10/14
摘要： An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.
摘要翻译：扩展的通用串行总线（EUSB）主机通过使用射频（RF）收发器或直接布线轨迹而不是一对传统的USB电缆减少了负载。减少负荷打开眼睛图案。 EUSB设备使用链接的直接内存访问（DMA）传输内部数据。 DMA控制器中的寄存器指向具有向量条目的向量表，每个向量表指向一个目的地和一个源。源是内存组的内存表。内存表有几个内存段的条目。每个存储表条目具有指向存储器段的指针和段的字节计数。一旦片段中的所有字节都被传送，该条目中的标志表示在存储器组中跟随其他内存段的时间。读取END标志时，向量表前进到下一个向量条目，并处理另一个内存段的内存组。

34. 发明申请

US20090037652A1 Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules 有权
标题翻译：命令排队智能存储传输管理器，用于将数据传送到原始NAND闪存模块
公开(公告)号：US20090037652A1
公开(公告)日：2009-02-05
申请号：US12252155
申请日：2008-10-15
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma
IPC分类号： G06F12/02 , G11C16/02
CPC分类号： G06F12/0246 , G06F3/0607 , G06F3/0632 , G06F12/0607 , G06F2212/1036 , G06F2212/7203 , G06F2212/7208 , G11C13/0004
摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.
摘要翻译：闪存模块具有通过NVM控制器通过物理块地址（PBA）总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘（SSD）的系统板上。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平，而在信道内的进一步的交织和重新映射可由NVM控制器执行。智能存储交换机使用SDRAM缓冲区，在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。剩余部分指向SDRAM中主机数据的位置。命令队列存储主机命令的Q，R。

35. 发明申请

US20080250195A1 Multi-Operation Write Aggregator Using a Page Buffer and a Scratch Flash Block in Each of Multiple Channels of a Large Array of Flash Memory to Reduce Block Wear 失效
标题翻译：多操作写入聚合器使用大量Flash存储器的多个通道中的每一个中的页面缓冲区和划痕闪存块来减少块磨损
公开(公告)号：US20080250195A1
公开(公告)日：2008-10-09
申请号：US12139842
申请日：2008-06-16
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F21/32 , G06F21/78 , G06F2212/1036 , G06F2212/7202 , G06F2212/7208 , G06K19/07 , G06K19/07354
摘要： A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.
摘要翻译：闪存系统具有可以并行访问的多个闪存芯片的通道。主机数据被多通道控制器处理器分配给一个通道，并且累积在多通道页缓冲器中。当到达页面缓冲区中的页面边界时，如果逻辑扇区地址（LSA）匹配，则页缓冲区将被写入目标物理块（如果已满）或与聚合闪存块（AFB）中的旧数据片段组合。因此，使用AFB聚集小片段，减少闪存块的擦除和磨损。发生STOP命令时，页面缓冲区被复制到AFB。每个通道都有一个或多个AFB，它们由AFB跟踪表进行跟踪。

36. 发明申请

US20080235443A1 Intelligent Solid-State Non-Volatile Memory Device (NVMD) System With Multi-Level Caching of Multiple Channels 失效
标题翻译：具有多通道多级缓存的智能固态非易失性存储器件（NVMD）系统
公开(公告)号：US20080235443A1
公开(公告)日：2008-09-25
申请号：US12115128
申请日：2008-05-05
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： G06F12/1416 , G06F3/0664 , G06F12/0851 , G06F12/0866 , G06F12/0897 , G06F21/32 , G06F21/78 , G06F21/79 , G06F2212/2022 , Y02D10/13
摘要： A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.
摘要翻译：闪存系统存储由逻辑块地址（LBA）寻址的非易失性存储器件（NVMD）中的数据块。 NVBA将对LBA进行重新配置以进行磨损均衡和坏块重定位。 NVMD在由NVMD控制器访问的通道中进行交织。 NVMD控制器具有缓存存储在该通道中的NVMD中的块的控制器高速缓存，而NVMD还包含高速缓存。多级缓存可以减少访问延迟。电源由NVMD控制器中的电源控制器以多级管理，为NVMD内的电源管理器设置电源策略。闪存系统中的多个NVMD控制器可以各自控制多个NVMD通道。具有NVMD的闪存系统可能包括用于安全性的指纹读取器。

37. 发明申请

US20080198545A1 Open-frame solid-state drive housing with intrinsic grounding to protect exposed chips 失效
标题翻译：开放式固态驱动器外壳，具有固有的接地保护裸露的芯片
公开(公告)号：US20080198545A1
公开(公告)日：2008-08-21
申请号：US12043398
申请日：2008-03-06
申请人： Jim Chin-Nan Ni , Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
发明人： Jim Chin-Nan Ni , Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F1/16
CPC分类号： G06F12/1416 , G06F3/0658 , G06F3/0679 , G06F21/32 , G06F21/78
摘要： An open-frame flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips, a controller chip, and a Serial AT-Attachment (SATA) connector soldered to it. The PCBA is only partially encased by left and right frames or by a U-shaped bracket frame. The frames have PCBA supports and guide posts that fit near edges of the PCBA. The frames do not cover the top and bottom of the PCBA, allowing chips on the PCBA to be ventilated by unblocked air flow. Screws that attach the PCBA to the frame have metal collars that ground the frame to the PCBA's ground plane. The screws form a current path to draw any electro-static-discharge (ESD) current off the frame and onto a PCBA ground. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the open frame.
摘要翻译：开放式闪存驱动器具有焊接到其上的具有闪存芯片的印刷电路板组件（PCBA），控制器芯片和串行AT附件（SATA）连接器。 PCBA仅部分地被左右框架或U形支架框架包围。这些框架具有PCBA支撑和适合PCBA边缘附近的导向柱。框架不覆盖PCBA的顶部和底部，允许PCBA上的芯片通过未阻塞的气流通风。将PCBA连接到框架上的螺钉具有金属套环，将框架接地到PCBA的接地平面。螺钉形成电流通道，以将任何静电放电（ESD）电流从框架上取出并插入PCBA接地。当SATA连接器插入主机时，主机接地会吸收由开放框架收集的ESD电流。

38. 发明授权

US07333364B2 Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory 失效
标题翻译：针对多位单元闪存的单元降级和参考电压调整
公开(公告)号：US07333364B2
公开(公告)日：2008-02-19
申请号：US11737336
申请日：2007-04-19
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G11C16/06
CPC分类号： G11C11/5621 , G11C11/5642 , G11C29/00 , G11C2211/5634 , G11C2211/5641
摘要： A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.
摘要翻译：闪存具有多级单元（MLC），每个单元可以存储多个位。当发生错误时，单元块可以降级到较少的位/单元，或用于存储关键数据（如引导代码）。来自单个MLC的位在多个页面之间进行分区，以使用错误校正码（ECC）来提高错误的可校正性。响应于校准寄存器，由参考电压发生器产生较高的参考电压，校准寄存器可编程为改变上参考电压。从较高参考电压产生一系列减小的参考值，并将其与位线电压进行比较。比较结果由翻译逻辑翻译，生成读取数据和编程过程中和编程不足的信号。降级的单元格使用相同的真值表，但生成较少的读取数据位。通过使用相同的子状态来读取降级和全密度MLC单元，噪声余量被不对称地改善。

39. 发明申请

US20110145489A1 HYBRID STORAGE DEVICE 审中-公开
标题翻译：混合存储设备
公开(公告)号：US20110145489A1
公开(公告)日：2011-06-16
申请号：US13032564
申请日：2011-02-22
申请人： I-Kang Yu , Charles C. Lee , Shimon Chen , Abraham C. Ma
发明人： I-Kang Yu , Charles C. Lee , Shimon Chen , Abraham C. Ma
IPC分类号： G06F12/00
CPC分类号： G06F3/0656 , G06F3/0613 , G06F3/068 , G06F3/0685 , G06F3/0688
摘要： A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode.
摘要翻译：混合存储设备包括固态盘（SDD）和至少一个硬盘驱动器（HDD）。混合存储设备具有至少两种操作模式：级联和安全。根据一个方面，混合存储设备的总容量是SSD和连接或大模式中的至少一个HDD的总和，而总容量是HDD在安全模式下的容量。

40. 发明授权

US07962836B1 Electronic data flash card with bose, ray-chaudhuri, hocquenghem (BCH) error detection/correction 有权
标题翻译：电子数据闪存卡与bose，ray-chaudhuri，hocquenghem（BCH）错误检测/纠正
公开(公告)号：US07962836B1
公开(公告)日：2011-06-14
申请号：US11657243
申请日：2007-01-24
申请人： Charles C. Lee , I-Kang Yu , Abraham C. Ma , Ming-Shiang Shen
发明人： Charles C. Lee , I-Kang Yu , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： H03M13/00
CPC分类号： H03M13/1545 , G06F7/724 , H03M13/152 , H03M13/1575
摘要： A Bose, Ray-Chaudhuri, Hocquenghem (BCH) decoder is employed in non-volatile memory applications for determining the number of errors and locating the errors in a page of information. The decoder includes a syndrome calculator responsive to a sector of information. The sector includes data and overhead, with the data being organized into data sections and the overhead being organized into overhead sections. The syndrome calculator generates a syndrome for each of the data sections. A root finder is coupled to receive the calculated syndrome and to generate at least two roots. A polynomial calculator responds to the two roots and generates at least two error addresses, each identifying a location in the data wherein the error lies.
摘要翻译： Bose，Ray-Chaudhuri，Hocquenghem（BCH）解码器用于非易失性存储器应用中，用于确定错误数量并将错误定位在一页信息中。解码器包括响应于信息扇区的综合征计算器。该部门包括数据和开销，数据被组织成数据部分，开销被组织成开销部分。综合征计算器为每个数据部分产生综合征。根取景器耦合以接收所计算的综合征并产生至少两个根。多项式计算器响应于两个根，并且生成至少两个错误地址，每个错误地址标识错误所在的数据中的位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式