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31. 外观设计

USD649141S1 Combination field radio modem and amplifier 有权
标题翻译：组合现场无线电调制解调器和放大器
公开(公告)号：USD649141S1
公开(公告)日：2011-11-22
申请号：US29361721
申请日：2010-05-13
申请人： E. Alex Thomas , Charles Branch
设计人： E. Alex Thomas , Charles Branch

32. 外观设计

USD641344S1 Heat, water, and shock resistant combination radio modem and amplifier 有权
标题翻译：热水，防震组合无线电调制解调器和放大器
公开(公告)号：USD641344S1
公开(公告)日：2011-07-12
申请号：US29361720
申请日：2010-05-13
申请人： E. Alex Thomas , Charles Branch
设计人： E. Alex Thomas , Charles Branch

33. 发明申请

US20070113048A1 Low-Power Co-Processor Architecture 有权
标题翻译：低功耗协处理器架构
公开(公告)号：US20070113048A1
公开(公告)日：2007-05-17
申请号：US11557755
申请日：2006-11-08
申请人： Marc Royer , Bharath Siravara , Steven Bartling , Charles Branch , Pedro Galabert , Neeraj Mogotra , Sunil Kamath
发明人： Marc Royer , Bharath Siravara , Steven Bartling , Charles Branch , Pedro Galabert , Neeraj Mogotra , Sunil Kamath
IPC分类号： G06F15/00 , G06F12/00
CPC分类号： G06F15/7864 , G06F9/3879 , Y02D10/13
摘要： A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing units of the co-processor, and also a bus slave circuit coupled to a system bus of the system, to selected ones of the memory blocks. The memory switch may be constructed as an array of multiplexers, controlled by control logic of the memory switch in response to the contents of a control register. The various processing units of the co-processor are each able to directly access one of the memory blocks, as controlled by the switch circuitry. Following processing of a block of data by one of the processing units, the memory switch associates the memory blocks with other functional units, thus moving data from one functional unit to another without requiring reading and rewriting of the data.
摘要翻译：公开了一种包括协处理器和存储器交换机资源的系统架构。存储器开关包括多个存储器块和用于可选择地将协处理器的处理单元耦合的开关电路，以及耦合到系统的系统总线的总线从属电路到选择的存储器块。存储器开关可以被构造为多路复用器的阵列，其由存储器开关的控制逻辑控制，以响应于控制寄存器的内容。协处理器的各种处理单元各自能够直接访问由开关电路控制的存储块之一。在由处理单元之一处理数据块之后，存储器开关将存储器块与其他功能单元相关联，从而将数据从一个功能单元移动到另一个功能单元，而不需要读取和重写数据。

34. 发明申请

US20070022339A1 Digital design component with scan clock generation 有权
标题翻译：具有扫描时钟产生的数字设计组件
公开(公告)号：US20070022339A1
公开(公告)日：2007-01-25
申请号：US11174193
申请日：2005-07-01
申请人： Charles Branch , Steven Bartling , Marc Royer , Cory Stewart
发明人： Charles Branch , Steven Bartling , Marc Royer , Cory Stewart
IPC分类号： G01R31/28
CPC分类号： G01R31/318552
摘要： A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.
摘要翻译：在扫描模式期间，触发器的主器件和从器件级分别以不重叠的时钟信号时钟，以消除数据输入扫描模式多路复用器。单独的，不重叠的时钟允许在扫描模式触发器链的扫描模式中消除保持违规，允许消除扫描模式数据路径中的延迟缓冲器。所得到的应用电路减少了电路面积，功耗和噪声产生。提供用于扫描模式时钟的时钟发生器以获得单独的非重叠扫描模式时钟。扫描模式时钟可以用切换触发器，脉冲发生器或时钟门控电路产生。

35. 发明申请

US20070022336A1 Digital storage element with enable signal gating 有权
标题翻译：具有使能信号门控的数字存储元件
公开(公告)号：US20070022336A1
公开(公告)日：2007-01-25
申请号：US11171528
申请日：2005-06-30
申请人： Charles Branch , Steven Bartling , Dharin Shah
发明人： Charles Branch , Steven Bartling , Dharin Shah
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318575 , G01R31/318594
摘要： A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.
摘要翻译：数字存储元件（例如，触发器或锁存器）包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。从机透明锁存器包括专用功能数据和扫描数据输出端口。还包括时钟门控元件，其基于被断言以禁用数字存储元件的使用的使能信号，将时钟关闭到从锁存器，而不是主器件透明锁存器。

36. 发明申请

US20070006109A1 Method and system for correcting signal integrity crosstalk violations 有权
标题翻译：纠正信号完整性串扰违规的方法和系统
公开(公告)号：US20070006109A1
公开(公告)日：2007-01-04
申请号：US11172284
申请日：2005-06-30
申请人： Steven Bartling , Marc Royer , Charles Branch
发明人： Steven Bartling , Marc Royer , Charles Branch
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A system and method for repairing crosstalk delays are disclosed herein. By modeling the change in effective capacitance, one may determine the delay attributable to crosstalk, and upsize cells in the failing net according to a mathematical formula in order to counter the delay.
摘要翻译：本文公开了用于修复串扰延迟的系统和方法。通过对有效电容的变化进行建模，可以根据数学公式确定归因于串扰的延迟，并根据数学公式升高故障网络中的单元，以抵消延迟。

37. 发明申请

US20070001733A1 Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality 有权
标题翻译：数字存储元件架构包括集成的2对1复用器功能
公开(公告)号：US20070001733A1
公开(公告)日：2007-01-04
申请号：US11172534
申请日：2005-06-30
申请人： Charles Branch , Steven Bartling , Dharin Shah
发明人： Charles Branch , Steven Bartling , Dharin Shah
IPC分类号： H03K3/00
CPC分类号： G11C29/48 , G11C29/32 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.
摘要翻译：数字存储元件包括从数据输入端口接收功能数据信号并从扫描输入端口扫描数据信号的主透明锁存器。数据输入端口耦合到双输入单输出多路复用器，其适于接收功能数据信号并选择性地输出功能数据信号之一。数字存储元件还包括耦合到主透明锁存器的从透明锁存器，从属透明锁存器包括专用功能数据和扫描数据输出端口。当在扫描模式下操作时，从属透明锁存器使用第一时钟信号，并且主透明锁存器使用第二时钟信号，其中第一和第二时钟信号是不重叠的。

38. 发明申请

US20050049623A1 Devices and techniques for a minimally invasive disc space preparation and implant insertion 有权
标题翻译：用于微创椎间隙准备和植入物插入的装置和技术
公开(公告)号：US20050049623A1
公开(公告)日：2005-03-03
申请号：US10653281
申请日：2003-09-02
申请人： Jeffrey Moore , James Duncan , Jeffrey Scifert , Charles Branch , Kevin Foley
发明人： Jeffrey Moore , James Duncan , Jeffrey Scifert , Charles Branch , Kevin Foley
IPC分类号： A61B17/00 , A61B17/16 , A61B17/32 , A61B17/34 , A61F2/44 , A61F2/46
CPC分类号： A61F2/4611 , A61B17/00234 , A61B17/1604 , A61B17/1631 , A61B17/1659 , A61B17/1671 , A61B17/3423 , A61B2017/320032 , A61F2/4455 , A61F2002/4622 , A61F2002/4623 , A61F2002/4624 , A61F2002/4627 , A61F2002/4635
摘要： Methods and instruments are provided for performing spinal disc space preparation and implant insertion in minimally invasive procedures. The instruments include cutting instruments and implant insertion instruments adapted for insertion through a minimally invasive access portal to a spinal disc space. The proximal portions of the instruments are adapted to facilitate viewing through a proximal end opening of the access portal with the instruments positioned through the access portal while also enhancing the surgeon's control of the distal working end of the instruments while in the disc space.
摘要翻译：提供方法和仪器用于在微创程序中进行脊椎椎间盘空间准备和植入物插入。仪器包括切割仪器和植入物插入器械，适于通过微创入口进入椎间盘空间进行插入。仪器的近端部分适于通过入口入口的近端开口进行观察，其中仪器通过进入门口定位，同时还增强外科医生在椎间盘空间期间仪器的远端工作端的控制。

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