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31. 发明授权

US07368806B2 Flip chip package with anti-floating structure 有权
标题翻译：倒装芯片封装，具有防浮动结构
公开(公告)号：US07368806B2
公开(公告)日：2008-05-06
申请号：US11296489
申请日：2005-12-08
申请人： Chien Liu , Meng-Jen Wang , Sheng-Tai Tsai
发明人： Chien Liu , Meng-Jen Wang , Sheng-Tai Tsai
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L24/16 , H01L23/3114 , H01L23/3128 , H01L23/4951 , H01L23/4952 , H01L24/81 , H01L2224/10135 , H01L2224/10165 , H01L2224/13099 , H01L2224/1403 , H01L2224/16 , H01L2224/81136 , H01L2224/81139 , H01L2224/81141 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/0401
摘要： A flip chip package with an anti-floating structure includes a leadframe, a flip chip, and a plurality of solders. The leadframe includes a plurality of leads and a fastening part. At least one locking hole is formed on an upper surface of the fastening part. The flip chip includes an active surface, and at least one locking protrusion and a plurality of bumps formed on the active surface. The locking protrusion is correspondingly plugged into the locking hole to act as an anti-floating structure for the flip chip package. When the solders are used for connecting the bumps with the leads by reflowing, the anti-floating structure will prevent the flip chip from floating up, and the solders will not generate necking after reflowing.
摘要翻译：具有防浮动结构的倒装芯片封装包括引线框，倒装芯片和多个焊料。引线框架包括多个引线和紧固部件。在紧固部的上表面上形成有至少一个锁定孔。倒装芯片包括有源表面，以及形成在有源表面上的至少一个锁定突起和多个凸块。锁定突起相应地插入到锁定孔中，以用作倒装芯片封装的防浮动结构。当焊料用于通过回流连接凸起与引线时，反浮动结构将防止倒装芯片浮起，并且焊料在回流之后不会产生颈缩。

32. 发明申请

US20060244115A1 Chip package structure and method for manufacturing the same 审中-公开
标题翻译：芯片封装结构及其制造方法
公开(公告)号：US20060244115A1
公开(公告)日：2006-11-02
申请号：US11313679
申请日：2005-12-22
申请人： Chien Liu , Meng-Jen Wang
发明人： Chien Liu , Meng-Jen Wang
IPC分类号： H01L23/02
CPC分类号： H01L23/4951 , H01L23/49517 , H01L23/49548 , H01L23/49568 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A chip package structure and a method for manufacturing the same are disclosed. The chip package structure comprises a carrier and a chip deposed on the carrier. The carrier comprises a heat-sinking pad, a plurality of pins, and at least two supporting bars, in which the heat-sinking pad has a carrying surface. The chip includes a plurality of bonding bumps flipped and connected to the heat-sinking pad, the pins, and the supporting bars of the carrier.
摘要翻译：公开了一种芯片封装结构及其制造方法。芯片封装结构包括载体和放置在载体上的芯片。载体包括散热垫，多个销和至少两个支撑条，其中散热垫具有承载表面。芯片包括翻转并连接到散热垫，引脚和载体的支撑杆的多个接合凸块。

33. 发明申请

US20060015984A1 Sun visor 审中-公开
标题翻译：遮阳板
公开(公告)号：US20060015984A1
公开(公告)日：2006-01-26
申请号：US10896224
申请日：2004-07-20
申请人： Chien Liu
发明人： Chien Liu
IPC分类号： A42B1/04
CPC分类号： A61F9/045 , A42B1/208
摘要： A sun visor includes two head band portions extended from a central visor portion and each having one or more coupling members to couple the head band portions together and to form a head encircling device and to adjustably attach the sun visor onto a head of a user. Two or more folding lines are formed between the center visor portion and each of the head band portions, and inclined relative to each other, to form a superposed portion between the center visor portion and the head band portions after the head band portions are folded relative to the center visor portion along the folding lines, and to form a frustum-shaped structure, but not a cylindrical-shaped structure for the head encircling device.
摘要翻译：遮阳板包括从中央遮阳板部分延伸的两个头带部分，每个具有一个或多个联接构件以将头带部分联接在一起并且形成头部环绕装置，并且将遮阳板可调节地附接到使用者的头部上。两个或多个折叠线形成在中心遮阳板部分和每个头带部分之间并相对于彼此倾斜，以在头带部分折叠相对之后在中心遮阳板部分和头带部分之间形成叠置部分并且形成截头锥形结构，而不是用于头部环绕装置的圆柱形结构。

34. 发明申请

US20050101053A1 Quad flat flip chip packaging process and leadframe therefor 有权
标题翻译：四平面倒装芯片封装工艺及其引线框架
公开(公告)号：US20050101053A1
公开(公告)日：2005-05-12
申请号：US10967910
申请日：2004-10-18
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/31 , H01L23/495 , H01L21/48
CPC分类号： H01L23/49558 , H01L23/3114 , H01L23/49586 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2224/05599
摘要： A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.
摘要翻译：提供了一种四平面倒装芯片封装工艺及其引线框架。牺牲膜附着在引线框架的引线上，用于在形成时限制凸块的程度并节省制造成本。此外，在回流步骤之后，牺牲膜可以从引线框架移除。因此，可以在成型步骤期间防止模塑料和导线之间的分层。

35. 发明授权

US07902650B2 Semiconductor package and method for manufacturing the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US07902650B2
公开(公告)日：2011-03-08
申请号：US12464334
申请日：2009-05-12
申请人： Chia Chien Hu , Chao Cheng Liu , Chien Liu , Chih Ming Chung
发明人： Chia Chien Hu , Chao Cheng Liu , Chien Liu , Chih Ming Chung
IPC分类号： H01L23/02 , H01L21/44
CPC分类号： H01L23/3128 , H01L21/561 , H01L23/16 , H01L24/48 , H01L24/97 , H01L2224/16 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01027 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2224/81 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/83 , H01L2924/00
摘要： A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.
摘要翻译：半导体封装包括载体，芯片，加强件和密封剂。芯片设置在载体上。加强件设置在芯片周围，直接接触载体，并安装在载体上。密封剂适于密封芯片和加强件。

36. 发明授权

US07425468B2 Method for making flip chip on leadframe package 有权
标题翻译：在引线框封装上制作倒装芯片的方法
公开(公告)号：US07425468B2
公开(公告)日：2008-09-16
申请号：US11636995
申请日：2006-12-12
申请人： Meng-Jen Wang , Chien Liu , Tsan-Sheng Huang
发明人： Meng-Jen Wang , Chien Liu , Tsan-Sheng Huang
IPC分类号： H01L21/00 , H01L21/44
CPC分类号： H01L24/11 , H01L24/81 , H01L2224/10135 , H01L2224/1147 , H01L2224/1181 , H01L2224/13099 , H01L2224/81011 , H01L2224/81136 , H01L2224/81139 , H01L2224/81194 , H01L2224/8121 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322
摘要： A flip chip on leadframe package and manufacturing method includes providing a leadframe having a plurality of inner leads; providing a chip having an active surface; forming a plurality of first bumps and at least one second bump on the active surface, the material of the first bumps is the same as the second bump, and the height of the second bump is lower than the first bumps; dipping the top of the first bumps in a flux, so that the second bump is not dipped with the flux; contacting the first bumps to the corresponding inner leads; proceeding with a reflow so that the first bumps are melted and connected to the corresponding inner leads, and the second bump is connected to the corresponding inner lead without being melted, to maintain a gap between the chip and the inner leads to prevent collapse of the first bumps.
摘要翻译：引线框封装的倒装芯片和制造方法包括提供具有多个内引线的引线框架; 提供具有活性表面的芯片; 在所述有源表面上形成多个第一凸块和至少一个第二凸块，所述第一凸块的材料与所述第二凸块相同，并且所述第二凸块的高度低于所述第一凸块; 将第一凸块的顶部浸入焊剂中，使得第二凸块不与焊剂一起浸入; 使所述第一凸起与相应的内引线接触; 继续进行回流，使得第一凸起熔化并连接到相应的内引线，并且第二凸起连接到相应的内引线而不熔化，以保持芯片和内引线之间的间隙，以防止第一个颠簸

37. 发明申请

US20080179739A1 FLIP CHIP PACKAGE WITH ANTI-FLOATING STRUCTURE 审中-公开
标题翻译：具有防浮动结构的FLIP芯片包装
公开(公告)号：US20080179739A1
公开(公告)日：2008-07-31
申请号：US12058816
申请日：2008-03-31
申请人： Chien Liu , Meng-Jen Wang , Sheng-Tai Tsai
发明人： Chien Liu , Meng-Jen Wang , Sheng-Tai Tsai
IPC分类号： H01L23/488
CPC分类号： H01L24/16 , H01L23/3114 , H01L23/3128 , H01L23/4951 , H01L23/4952 , H01L24/81 , H01L2224/10135 , H01L2224/10165 , H01L2224/13099 , H01L2224/1403 , H01L2224/16 , H01L2224/81136 , H01L2224/81139 , H01L2224/81141 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/0401
摘要： A flip chip package with an anti-floating structure includes a leadframe, a flip chip, and a plurality of solders. The leadframe includes a plurality of leads and a fastening part. At least one locking hole is formed on an upper surface of the fastening part. The flip chip includes an active surface, and at least one locking protrusion and a plurality of bumps formed on the active surface. The locking protrusion is correspondingly plugged into the locking hole to act as an anti-floating structure for the flip chip package. When the solders are used for connecting the bumps with the leads by reflowing, the anti-floating structure will prevent the flip chip from floating up, and the solders will not generate necking after reflowing.
摘要翻译：具有防浮动结构的倒装芯片封装包括引线框，倒装芯片和多个焊料。引线框架包括多个引线和紧固部件。在紧固部的上表面上形成有至少一个锁定孔。倒装芯片包括有源表面，以及形成在有源表面上的至少一个锁定突起和多个凸块。锁定突起相应地插入到锁定孔中，以用作倒装芯片封装的防浮动结构。当焊料用于通过回流连接凸起与引线时，反浮动结构将防止倒装芯片浮起，并且焊料在回流之后不会产生颈缩。

38. 发明申请

US20070172981A1 Method for making flip chip on leadframe package 有权
标题翻译：在引线框封装上制作倒装芯片的方法
公开(公告)号：US20070172981A1
公开(公告)日：2007-07-26
申请号：US11636995
申请日：2006-12-12
申请人： Meng-Jen Wang , Chien Liu , Tsan-Sheng Huang
发明人： Meng-Jen Wang , Chien Liu , Tsan-Sheng Huang
IPC分类号： H01L21/60
CPC分类号： H01L24/11 , H01L24/81 , H01L2224/10135 , H01L2224/1147 , H01L2224/1181 , H01L2224/13099 , H01L2224/81011 , H01L2224/81136 , H01L2224/81139 , H01L2224/81194 , H01L2224/8121 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322
摘要： The present invention relates to a flip chip on leadframe package and the method for making the same. The method comprises: (a) providing a leadframe having a plurality of inner leads; (b) providing a chip having an active surface; (c) forming a plurality of first bumps and at least one second bump on the active surface of the chip, wherein the material of the first bumps is same as that of the second bump, and the height of the second bump is lower than that of the first bumps; (d) dipping the top of the bumps in a flux so that the first bumps are dipped with the flux, and the second bump is not dipped with the flux; (e) contacting the first bumps to the corresponding inner leads; (f) proceeding with a reflow step so that the first bumps are melted and connected to the corresponding inner leads, and the second bump is connected to the corresponding inner lead without being melted so as to maintain the gap between the chip and the inner leads. As a result, the first bumps will not collapse and the yield of the flip chip bonding is raised.
摘要翻译：本发明涉及一种引线框封装上的倒装芯片及其制造方法。该方法包括：（a）提供具有多个内引线的引线框架; （b）提供具有活性表面的芯片; （c）在所述芯片的有源表面上形成多个第一凸块和至少一个第二凸块，其中所述第一凸块的材料与所述第二凸块的材料相同，并且所述第二凸块的高度低于所述第二凸块的高度的第一个颠簸; （d）将焊盘的顶部浸入焊剂中，使得第一凸块与焊剂一起浸渍，并且第二凸块不与焊剂一起浸渍; （e）使所述第一凸块与相应的内引线接触; （f）进行回流工序，使第一凸块熔化并连接到相应的内引线，第二凸块连接到相应的内引线而不熔化，以保持芯片与内引线之间的间隙。结果，第一凸起不会塌陷，并且提高了倒装芯片接合的产量。

39. 发明申请

US20060290769A1 Print head pulsing techniques for multicolor printers 有权
公开(公告)号：US20060290769A1
公开(公告)日：2006-12-28
申请号：US11159880
申请日：2005-06-23
申请人： Chien Liu , William Vetterling
发明人： Chien Liu , William Vetterling
IPC分类号： B41J2/40
CPC分类号： B41J2/355 , B41J2/36
摘要： In one aspect of the invention there is disclosed a multicolor thermal imaging system wherein different heating elements on a thermal print head can print on different color-forming layers of a multicolor thermal imaging member in a single pass. The line-printing time is divided into portions, each of which is divided into a plurality of subintervals. All of the pulses within the portions have the same energy. In one embodiment, every pulse has the same amplitude and duration. Different colors are selected for printing during the different portions by varying the fraction of subintervals that contain pulses. This technique allows multiple colors to be printed using a thermal print head with a single strobe signal line. Pulsing patterns may be chosen to reduce the coincidence of pulses provided to multiple print head elements, thereby reducing the peak power requirements of the print head.

40. 发明申请

US20060270552A1 Thermal imaging system 有权
公开(公告)号：US20060270552A1
公开(公告)日：2006-11-30
申请号：US11397251
申请日：2006-04-03
申请人： Jayprakash Bhatt , Daniel Bybell , F. Courell , Anemarie DeYoung , Chien Liu , Stephen Telfer , Jay Thornton , William Vetterling
发明人： Jayprakash Bhatt , Daniel Bybell , F. Courell , Anemarie DeYoung , Chien Liu , Stephen Telfer , Jay Thornton , William Vetterling
IPC分类号： B41M5/24
CPC分类号： B41J2/32 , B41J2/36 , B41M5/3275 , B41M5/3335 , B41M5/3336 , B41M5/34 , B41M5/40 , B41M5/42 , B41M5/426 , B41M5/44 , B41M2205/04 , B41M2205/38 , G03C1/52
摘要： A multicolor imaging system is described wherein at least two, and preferably three, different image-forming layers of a thermal imaging member are addressed at least partially independently by a thermal printhead or printheads from the same surface of the imaging member by controlling the temperature of the thermal printhead(s) and the time thermal energy is applied to the image-forming layers. Each color of the thermal imaging member can be printed alone or in selectable proportion to the other color(s). Novel thermal imaging members are also described.

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