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31. 发明申请

US20080220588A1 STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI) 有权
公开(公告)号：US20080220588A1
公开(公告)日：2008-09-11
申请号：US12125175
申请日：2008-05-22
申请人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
IPC分类号： H01L21/46
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

32. 发明申请

US20080171423A1 LOW-COST STRAINED SOI SUBSTRATE FOR HIGH-PERFORMANCE CMOS TECHNOLOGY 有权
标题翻译：用于高性能CMOS技术的低成本应变SOI衬底
公开(公告)号：US20080171423A1
公开(公告)日：2008-07-17
申请号：US11622543
申请日：2007-01-12
申请人： Meikei Ieong , Douglas C. La Tulipe , Leathen Shi , Anna W. Topol , James Vichiconti , Albert M. Young
发明人： Meikei Ieong , Douglas C. La Tulipe , Leathen Shi , Anna W. Topol , James Vichiconti , Albert M. Young
IPC分类号： H01L21/20
CPC分类号： H01L21/02658 , H01L21/02667 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/78 , H01L29/7843
摘要： A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.
摘要翻译：提供了一种制造应变绝缘体上半导体（SSOI）结构的成本有效和简单的方法，其避免了外延生长和随后的晶片接合处理步骤。根据本发明，使用应变记忆技术在SOI衬底上产生应变半导体区域。形成在应变半导体区域上的晶体管具有更高的载流子迁移率，因为Si区域已经变形。本发明的方法包括（i）离子注入以产生薄的非晶化层，（ii）在非晶化层上沉积高应力膜，（iii）热退火以使非晶化层重结晶，和（iv）去除应力电影。由于在再结晶过程中SOI衬底处于应力状态，所以最终的半导体层也将受到应力。应力的量和应力的极性（拉伸或压缩）可以通过应力膜的类型和厚度来控制。

33. 发明申请

US20060194414A1 Low temperature fusion bonding with high surface energy using a wet chemical treatment 失效
标题翻译：使用湿化学处理，具有高表面能的低温熔融粘合
公开(公告)号：US20060194414A1
公开(公告)日：2006-08-31
申请号：US11411395
申请日：2006-04-26
申请人： Kevin Chan , Kathryn Guarini , Erin Jones , Antonio Saavedra , Leathen Shi , Dinkar Singh
发明人： Kevin Chan , Kathryn Guarini , Erin Jones , Antonio Saavedra , Leathen Shi , Dinkar Singh
IPC分类号： H01L21/30
CPC分类号： H01L21/02052 , H01L21/02164 , H01L21/02343 , H01L21/2007 , H01L21/306 , H01L21/3105 , H01L21/31612 , H01L21/31662 , H01L21/76251
摘要： Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.
摘要翻译：描述了涉及NH 4 OH的湿化学表面处理，其能够使诸如半导体（例如Si）的两个晶片与绝缘体（例如，SiO 2）的极强直接接合，在低温（小于或等于400℃）。使用这些表面处理中的一些已经实现了键合界面的高达〜4835±675mJ / m 2的表面能。该值与显着更高的处理温度（小于1000℃）报告的值相当。本文还可以实现具有优异产率和约2500mJ / m 2的表面能的无空隙键合界面。

34. 发明申请

US20060186416A1 MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 有权
标题翻译：多层和晶体平面取向半导体基板
公开(公告)号：US20060186416A1
公开(公告)日：2006-08-24
申请号：US10906557
申请日：2005-02-24
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
摘要翻译：绝缘体上半导体衬底及其制造方法。所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向，第一晶体方向与第二晶体方向不同。

35. 发明申请

US20060001088A1 Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 失效
标题翻译：拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）
公开(公告)号：US20060001088A1
公开(公告)日：2006-01-05
申请号：US10883443
申请日：2004-07-01
申请人： Kevin Chan , Jack Chu , Kern Rim , Leathen Shi
发明人： Kevin Chan , Jack Chu , Kern Rim , Leathen Shi
IPC分类号： H01L21/00 , H01L31/0392
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate comprising a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer. Specifically, the method includes forming a first multilayered structure comprising at least a tensile-strained SiGe alloy layer located above a relaxed SiGe alloy layer, wherein the tensile-strained SiGe alloy contains a lower Ge content than the relaxed SiGe alloy layer; bonding the first multilayered structure to an insulating layer of a second multilayered structure on a surface opposite the relaxed SiGe alloy layer; and removing the relaxed SiGe alloy layer.
摘要翻译：提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。具体地说，该方法包括形成至少包含位于松弛SiGe合金层上方的拉伸应变SiGe合金层的第一多层结构，其中拉伸应变SiGe合金含有比松弛SiGe合金层低的Ge含量; 将第一多层结构结合到与松弛SiGe合金层相对的表面上的第二多层结构的绝缘层; 并去除松弛的SiGe合金层。

36. 发明授权

US06660598B2 Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region 失效
标题翻译：形成具有稀疏沟道区的完全耗尽的SOI（绝缘体上硅）MOSFET的方法
公开(公告)号：US06660598B2
公开(公告)日：2003-12-09
申请号：US10084550
申请日：2002-02-26
申请人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L21336
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.
摘要翻译：提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。根据本发明的方法，首先在SOI层顶部形成至少一个虚拟栅极区域。虚拟栅极区域至少包括牺牲多晶硅区域和位于牺牲多晶硅区域的侧壁上的第一氮化物间隔物。接下来，形成与伪栅极区的上表面共面的氧化物层，然后除去牺牲多晶硅区域，以露出SOI层的一部分。在SOI层的暴露部分中形成一个变薄的器件沟道区，此后在第一氮化物间隔物的暴露的壁上形成内部氮化物间隔物。接下来，在减薄的器件沟道区上形成栅极区，然后除去氧化物层，以便暴露出SOI层的比较器件沟道区更厚的部分。

37. 发明授权

US06399406B2 Encapsulated MEMS band-pass filter for integrated circuits and method of fabrication thereof 失效
标题翻译：用于集成电路的封装的MEMS带通滤波器及其制造方法
公开(公告)号：US06399406B2
公开(公告)日：2002-06-04
申请号：US09840264
申请日：2001-04-23
申请人： Kevin K. Chan , Christopher Jhanes , Leathen Shi , James L. Speidell , James F. Ziegler
发明人： Kevin K. Chan , Christopher Jhanes , Leathen Shi , James L. Speidell , James F. Ziegler
IPC分类号： H01L2100
CPC分类号： H03H3/0072 , H03H9/1057 , H03H9/2463 , H03H9/465
摘要： Communication signal mixing and filtering systems and methods utilizing an encapsulated micro electro-mechanical system (MEMS) device. Furthermore, disclosed is a method of fabricating a simple, unitarily constructed micro electromechanical system (MEMS) device which combines the steps of signal mixing and filtering, and which is smaller, less expensive and more reliable in construction and operation than existing devices currently employed in the technology.
摘要翻译：使用封装的微机电系统（MEMS）装置的通信信号混合和滤波系统和方法。此外，公开了一种制造简单，单一构造的微机电系统（MEMS）装置的方法，其组合了信号混合和滤波的步骤，并且其结构和操作更小，更便宜和更可靠，与目前在技术。

38. 发明授权

US08492838B2 Isolation structures for SOI devices with ultrathin SOI and ultrathin box 有权
标题翻译：具有超薄SOI和超薄盒的SOI器件的隔离结构
公开(公告)号：US08492838B2
公开(公告)日：2013-07-23
申请号：US12618871
申请日：2009-11-16
申请人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/76264 , H01L21/76232
摘要： Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.
摘要翻译：浅埋沟形成在埋入绝缘体部分和顶部半导体部分的垂直堆叠周围。介电材料层直接沉积在顶部半导体部分的侧壁上。通过用诸如氧化硅的介电材料填充浅沟槽来形成浅沟槽隔离结构。在平坦化之后，顶部半导体部分被电介质材料层横向接触并包围。介电材料层防止在湿蚀刻期间在掩埋绝缘体部分下面的手柄基板的暴露，从而确保手柄基板和随后形成在顶部半导体部分上的栅电极之间的电隔离。

39. 发明申请

US20130105981A1 FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING 有权
标题翻译：用于基板结合的平坦化基板表面
公开(公告)号：US20130105981A1
公开(公告)日：2013-05-02
申请号：US13285443
申请日：2011-10-31
申请人： Edward C. Cooney, III , James S. Dunn , Dale W. Martin , Charles F. Musante , BethAnn Rainey , Leathen Shi , Edmund J. Sprogis , Cornelia K. Tsang
发明人： Edward C. Cooney, III , James S. Dunn , Dale W. Martin , Charles F. Musante , BethAnn Rainey , Leathen Shi , Edmund J. Sprogis , Cornelia K. Tsang
IPC分类号： H01L23/48 , H01L21/58
CPC分类号： H01L23/4825 , H01L21/6835 , H01L21/76819 , H01L22/32 , H01L22/34 , H01L23/5223 , H01L23/5283 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/80 , H01L24/81 , H01L29/1054 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2221/68381 , H01L2224/0361 , H01L2224/0401 , H01L2224/05166 , H01L2224/05187 , H01L2224/05567 , H01L2224/05624 , H01L2224/05687 , H01L2224/06181 , H01L2224/08225 , H01L2224/131 , H01L2224/73251 , H01L2224/80011 , H01L2224/80013 , H01L2224/80075 , H01L2224/80203 , H01L2224/804 , H01L2224/80487 , H01L2224/80896 , H01L2224/80907 , H01L2224/80948 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13062 , H01L2924/15788 , H01L2924/014 , H01L2224/08 , H01L2224/16 , H01L2924/05432 , H01L2924/053 , H01L2924/01031 , H01L2924/01033 , H01L2924/04941 , H01L2924/00 , H01L2224/05552
摘要： Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.
摘要翻译：用于粘结衬底表面，键合衬底组件和用于键合衬底组件的设计结构的方法。使用器件基板的第一表面形成产品芯片的器件结构。在产品芯片上形成用于器件结构的互连结构的布线层。布线层被平坦化。临时处理晶片可移除地结合到平坦化的布线层。响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面被结合到最终的手柄基板。然后将临时手柄晶片从组件中取出。

40. 发明申请

US20120312452A1 ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES 审中-公开
标题翻译：用于基板之间的平面结合的自适应块
公开(公告)号：US20120312452A1
公开(公告)日：2012-12-13
申请号：US13591286
申请日：2012-08-22
申请人： Dechao Guo , Fei Liu , Leathen Shi , Keith Kwong Hon Wong
发明人： Dechao Guo , Fei Liu , Leathen Shi , Keith Kwong Hon Wong
IPC分类号： H01L21/683 , B32B41/00
CPC分类号： H01L21/6833 , B32B37/0007 , B32B2457/14 , Y10T156/1002
摘要： An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded.
摘要翻译：静电卡盘包括独立偏置的导电卡盘元件的阵列，传感器 - 导体组件的阵列，和/或传感器 - 导体组件阵列和至少一个电动卡盘的组合。独立地或嵌入传感器 - 导体组件中的导电卡盘元件被静电地独立地偏置以补偿其上的衬底的弯曲和/或翘曲，使得衬底可以与平坦表面结合。可以使用单个静电卡盘来减少要接合的两个基板中的一个的弯曲和翘曲，或者可以使用两个静电卡盘来最小化要接合的两个基板的弯曲和翘曲。

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