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31. 发明申请

US20050186738A1 High-density NROM-FINFET 失效
标题翻译：高密度NROM-FINFET
公开(公告)号：US20050186738A1
公开(公告)日：2005-08-25
申请号：US11073017
申请日：2005-03-04
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L29/792 , H01R11/22 , H01R13/62
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , Y10S257/903 , Y10S257/904 , Y10S257/905
摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.
摘要翻译：具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中，肋骨肋具有基本上矩形的形状，肋的上侧和肋侧面相对。存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。

32. 发明授权

US06180458B2 Method of producing a memory cell configuration 失效
标题翻译：产生存储单元配置的方法
公开(公告)号：US06180458B2
公开(公告)日：2001-01-30
申请号：US09095260
申请日：1998-06-10
申请人： Wolfgang Krautschneider , Franz Hofmann , Wolfgang Roesner
发明人： Wolfgang Krautschneider , Franz Hofmann , Wolfgang Roesner
IPC分类号： H01L21336
CPC分类号： H01L27/1128 , H01L27/112
摘要： A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed on the side walls of the trenches. The memory cell configuration can be produced with a mean area requirement for each memory cell of 1 F2, where F is the minimum structure size.
摘要翻译：存储单元配置包括具有平面MOS晶体管的第一存储单元和具有垂直MOS晶体管的第二存储单元。平面MOS晶体管设置在平行的带状沟槽的底部和顶部上。垂直MOS晶体管设置在沟槽的侧壁上。存储单元配置可以用1 F2的每个存储单元的平均面积要求来生成，其中F是最小结构尺寸。

33. 发明授权

US5736761A DRAM cell arrangement and method for its manufacture 失效
标题翻译： DRAM单元布置及其制造方法
公开(公告)号：US5736761A
公开(公告)日：1998-04-07
申请号：US645503
申请日：1996-05-14
申请人： Lothar Risch , Franz Hofmann , Wolfgang Roesner , Wolfgang Krautschneider
发明人： Lothar Risch , Franz Hofmann , Wolfgang Roesner , Wolfgang Krautschneider
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capacitor dielectric (16), which is in particular a ferroelectric or paraelectric layer, is arranged on at least the second source/drain region and a capacitor plate (17) is arranged on the dielectric, so that the second source/drain region (3) acts additionally as a memory node. The DRAM cell arrangement can be manufactured with a memory cell surface of 4 F.sup.2.
摘要翻译： DRAM单元布置对每个存储单元具有一个垂直MOS晶体管，其第一源极/漏极区域邻接沟槽位线（5），其栅极电极（13）与沟槽字线连接，并且其第二源极/漏极区域（3）邻接基板主表面（1）。至少在第二源极/漏极区域上布置有特别是铁电体或者顺电层的电容器电介质（16），并且电容器板（17）布置在电介质上，使得第二源极/漏极区域 3）另外作为存储器节点。可以利用4F2的存储单元表面来制造DRAM单元布置。

34. 发明授权

US5385852A Method for manufacturing vertical MOS transistors 失效
标题翻译：制造垂直MOS晶体管的方法
公开(公告)号：US5385852A
公开(公告)日：1995-01-31
申请号：US163523
申请日：1993-12-09
申请人： Klaus-Guenter Oppermann , Wolfgang Roesner , Franz Hofmann
发明人： Klaus-Guenter Oppermann , Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7813 , Y10S148/126
摘要： For manufacturing vertical MOS transistors, doped regions for a drain (11), well (3), and source (4) are formed in a vertical sequence in a substrate (1). Using a Si.sub.3 N.sub.4 mask (5), trenches (6) are etched perpendicular to the surface of the substrate (1). The trenches isolate the source (4) and well (3) structure, and are filled with doped polysilicon and are closed in an upper region with an insulation structure (8) in self-aligned fashion on the basis of local oxidation. The insulation structure (8) projects laterally beyond the trenches (6). Using the insulation structure (8) as an etching mask, via contact holes (9), that are provided with a metallization for contacting the source (4) and the well (3), are opened down into the well (3) between neighboring trenches (6).
摘要翻译：为了制造垂直MOS晶体管，在衬底（1）中以垂直顺序形成用于漏极（11），阱（3）和源极（4）的掺杂区域。使用Si 3 N 4掩模（5），垂直于衬底（1）的表面蚀刻沟槽（6）。沟槽隔离源（4）和阱（3）结构，并且填充有掺杂多晶硅，并且在基于局部氧化的自对准方式下在具有绝缘结构（8）的上部区域中封闭。绝缘结构（8）横向延伸超过沟槽（6）。使用绝缘结构（8）作为蚀刻掩模，通过接触孔（9），其具有用于接触源（4）和阱（3）的金属化，在邻近的孔（3）之间向下打开沟槽（6）。

35. 发明授权

US07893519B2 Integrated circuit with conductive structures 有权
标题翻译：具有导电结构的集成电路
公开(公告)号：US07893519B2
公开(公告)日：2011-02-22
申请号：US12128336
申请日：2008-05-28
申请人： Franz Hofmann
发明人： Franz Hofmann
IPC分类号： H01L29/00
CPC分类号： H01L27/11521 , H01L27/11524
摘要： An integrated circuit includes an array of transistors and a number of wordlines, where individual ones of the wordlines are coupled to a number of the transistors in the array. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.
摘要翻译：集成电路包括晶体管阵列和多个字线，其中字线中的单个字线与阵列中的多个晶体管耦合。与字线绝缘的导电结构被布置在字线下方的层中，并且布置在晶体管之间。

36. 发明授权

US07767567B2 Method of forming a semiconductor memory device and semiconductor memory device 有权
标题翻译：形成半导体存储器件和半导体存储器件的方法
公开(公告)号：US07767567B2
公开(公告)日：2010-08-03
申请号：US11541404
申请日：2006-09-29
申请人： Josef Willer , Franz Hofmann
发明人： Josef Willer , Franz Hofmann
IPC分类号： H01L21/3205
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.
摘要翻译：存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。在为源极线提供的区域中的间隔件之间形成开口。施加牺牲层以填充开口并且随后被图案化。间隙填充有介电材料的平坦化层。去除牺牲层的残余物并施加导电材料以形成源极线。

37. 发明申请

US20090309152A1 Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same 有权
标题翻译：具有接触区域的集成电路及其制造方法
公开(公告)号：US20090309152A1
公开(公告)日：2009-12-17
申请号：US12137388
申请日：2008-06-11
申请人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
发明人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L21/28273 , H01L21/8221 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
摘要翻译：在一个实施例中，提供了具有存储单元布置的集成电路。存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移基材的主要加工表面。

38. 发明申请

US20080096352A1 Method of forming a semiconductor memory device and semiconductor memory device 有权
标题翻译：形成半导体存储器件和半导体存储器件的方法
公开(公告)号：US20080096352A1
公开(公告)日：2008-04-24
申请号：US11541404
申请日：2006-09-29
申请人： Josef Willer , Franz Hofmann
发明人： Josef Willer , Franz Hofmann
IPC分类号： H01L21/336
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.
摘要翻译：存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。在为源极线提供的区域中的间隔件之间形成开口。施加牺牲层以填充开口并且随后被图案化。间隙填充有介电材料的平坦化层。去除牺牲层的残余物并施加导电材料以形成源极线。

39. 发明授权

US07307865B2 Integrated read-only memory, method for operating said read-only memory and corresponding production method 有权
标题翻译：集成只读存储器，用于操作所述只读存储器的方法和相应的制造方法
公开(公告)号：US07307865B2
公开(公告)日：2007-12-11
申请号：US10505320
申请日：2003-02-17
申请人： Franz Hofmann , Richard Johannes Luyken , Till Schlosser
发明人： Franz Hofmann , Richard Johannes Luyken , Till Schlosser
IPC分类号： G11C17/00
CPC分类号： H01L27/28 , H01L27/2436 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/147
摘要： An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer is provided between the drain connections and the electrode, whose electric resistance can be changed under the effect of a configuration voltage or current. The layer may be applied in a backend process.
摘要翻译：具有选择晶体管的集成只读存储器，每个具有漏极连接和用于馈送诸如电压或电流的电信号的电极连接。在漏极连接和电极之间设置一层，其电阻可以在配置电压或电流的作用下改变。该层可以应用在后端进程中。

40. 发明授权

US07157767B2 Semiconductor memory element, semiconductor memory arrangement, method for fabricating a semiconductor memory element and method for operating a semiconductor memory element 有权
标题翻译：半导体存储元件，半导体存储装置，半导体存储元件的制造方法以及半导体存储元件的操作方法
公开(公告)号：US07157767B2
公开(公告)日：2007-01-02
申请号：US10486184
申请日：2002-09-02
申请人： Michael Specht , Franz Hofmann
发明人： Michael Specht , Franz Hofmann
IPC分类号： H01L29/788
CPC分类号： H01L29/513 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/518 , H01L29/66825 , H01L29/7883
摘要： A semiconductor memory element has a substrate, in which a source region and a drain region are formed, a floating gate electrically insulated from the substrate, and a tunnel barrier arrangement, via which charging or discharging of the floating gate can be performed. It is possible to alter the conductivity of a channel between source and drain regions by charging or discharging the floating gate. A source line is electrically conductively connected to the source region and controls the charge transmission of the tunnel barrier arrangement.
摘要翻译：半导体存储元件具有形成源极区域和漏极区域的基板，与基板电绝缘的浮动栅极以及可以进行浮置栅极的充电或放电的隧道势垒装置。通过对浮动栅极进行充电或放电，可以改变源区和漏区之间的沟道的导电性。源极线导电地连接到源极区域并控制隧道势垒装置的电荷传输。

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