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31. 发明授权

US07337101B1 Method and apparatus for extending the capabilities of tools used for designing systems on programmable logic devices to satisfy timing requirements 有权
标题翻译：用于扩展用于在可编程逻辑器件上设计系统的工具的能力以满足定时要求的方法和装置
公开(公告)号：US07337101B1
公开(公告)日：2008-02-26
申请号：US10417702
申请日：2003-04-17
申请人： Steven Perry , Gregor Nixon , Ziad Abu-Lebdeh , Alasdair Scott , Philippe Marti
发明人： Steven Perry , Gregor Nixon , Ziad Abu-Lebdeh , Alasdair Scott , Philippe Marti
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a programmable logic device (PLD) includes translating a timing requirement of the system into a geographical constraint. Resources on the PLD are fitted onto locations on the PLD in response to the geographical constraint.
摘要翻译：用于在可编程逻辑器件（PLD）上设计系统的方法包括将系统的定时要求转换为地理约束。 PLD上的资源适应于PLD的位置以响应地理约束。

32. 发明授权

US08825730B1 Matrix decomposition using dataflow techniques 有权
标题翻译：使用数据流技术进行矩阵分解
公开(公告)号：US08825730B1
公开(公告)日：2014-09-02
申请号：US13252562
申请日：2011-10-04
申请人： Steven Perry , Coleman C. Cheung
发明人： Steven Perry , Coleman C. Cheung
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： Efficient and scalable circuitry for performing Cholesky decomposition is based on a dataflow style architecture which uses self-timed circuitry and eliminates the need for complicated state machines. Calculations are ordered such that partial sums of products are created in parallel subject to data dependency requirements, allowing a single accumulator to perform the summation. A Vector FIFO receives a partial sum of products from a vector processing engine. A Feedback FIFO stores partial results and feeds the partial results back to the data path based on signals from a dataflow controller. The circuitry is flexible to allow different matrix sizes, speed grades, and target frequencies without recompilation.
摘要翻译：用于执行Cholesky分解的高效和可扩展的电路基于使用自定时电路的数据流风格架构，并且不需要复杂的状态机。按照数据依赖性要求并行创建产品的部分和来进行计算，允许单个累加器执行求和。向量FIFO从矢量处理引擎接收产品的部分和。反馈FIFO存储部分结果，并且基于来自数据流控制器的信号将部分结果反馈给数据路径。该电路灵活，允许不同的矩阵尺寸，速度等级和目标频率，无需重新编译。

33. 发明授权

US08793629B1 Method and apparatus for implementing carry chains on FPGA devices 有权
标题翻译：用于在FPGA器件上实现进位链的方法和装置
公开(公告)号：US08793629B1
公开(公告)日：2014-07-29
申请号：US12987519
申请日：2011-01-10
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5054
摘要： A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partitioned adder having a plurality of sub-adders each registering an intermediate result.
摘要翻译：用于设计要在现场可编程门阵列（FPGA）上实现的系统的方法包括从系统的中间表示识别加法器。目标设备上的组件被指定为支持并实现加法器作为具有多个分别加入中间结果的子加法器的分区加法器。

34. 发明授权

US08739108B1 Method and apparatus for implementing loop-based control in an electronic design automation tool 有权
标题翻译：在电子设计自动化工具中实现循环控制的方法和装置
公开(公告)号：US08739108B1
公开(公告)日：2014-05-27
申请号：US13199588
申请日：2011-09-03
申请人： Steven Perry , Simon Finn
发明人： Steven Perry , Simon Finn
IPC分类号： G06F15/04 , G06F17/50
CPC分类号： G06F17/5045
摘要： A selectable block in a graphical user interface of an electric design automation tool for generating a design of a system on a target device includes a token passing unit operable to pass a token through one of a first output port and second output port in response to a result from a loop test. The selectable block also includes a counter operable to increment a step value in response to the selectable block receiving the token at a first input port.
摘要翻译：用于在目标设备上生成系统的设计的电气设计自动化工具的图形用户界面中的可选块包括令牌传递单元，其可操作以响应于第一输出端口和第二输出端口将令牌传递通过第一输出端口和第二输出端口中的一个来自循环测试。可选块还包括计数器，可操作以响应于在第一输入端口处接收令牌的可选择块增加步长值。

35. 发明授权

US08499262B1 Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool 有权
标题翻译：用电子设计自动化工具实现可参数化过滤块的方法和装置
公开(公告)号：US08499262B1
公开(公告)日：2013-07-30
申请号：US12807959
申请日：2010-09-17
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5045 , H03H17/0294 , H03H17/0664
摘要： An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array. (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block selectable by a designer to include in the block based schematic to represent a component in the design that filters data. The EDA tool includes a design adjustment unit to automatically modify previously programmed and selected components and wires in the block based schematic without input from the designer upon determining a change made to the parameterizable filter block by the designer.
摘要翻译：一种用于在现场可编程门阵列上生成系统设计的电气设计自动化（EDA）工具。（FPGA）包括用于创建基于块的原理图的图形用户界面。 EDA工具包括一个库，其中包括可由设计者选择的可参数化过滤器块，以包含在基于块的原理图中，以表示过滤数据的设计中的组件。 EDA工具包括设计调整单元，用于在确定由设计者对可参数化滤波器块进行的改变时，自动修改基于块的原理图中的先前编程和选择的部件和导线，而无需设计者的输入。

36. 发明授权

US08468476B1 Method and apparatus for designing a system on multiple field programmable gate array device types 有权
公开(公告)号：US08468476B1
公开(公告)日：2013-06-18
申请号：US13053178
申请日：2011-03-21
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.

37. 发明授权

US07895549B1 Method and apparatus for implementing a processor interface block with an electronic design automation tool 有权
标题翻译：一种用电子设计自动化工具实现处理器接口块的方法和装置
公开(公告)号：US07895549B1
公开(公告)日：2011-02-22
申请号：US11986606
申请日：2007-11-23
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/68
摘要： An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.
摘要翻译：用于在现场可编程门阵列（FPGA）上生成系统设计的电气设计自动化（EDA）工具包括一个库，其包括由设计者可选择的处理器接口块，以表示处理器可访问的设计中的组件。 EDA工具还包括处理器接口电路生成单元，用于在设计中自动生成电路以支持处理器接口块，而无需设计者的输入。

38. 发明授权

US07234044B1 Processor registers having state information 有权
标题翻译：具有状态信息的处理器寄存器
公开(公告)号：US07234044B1
公开(公告)日：2007-06-19
申请号：US10727850
申请日：2003-12-03
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F9/302 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30094 , G06F9/30105 , G06F9/3012 , G06F9/30123 , G06F9/321 , G06F9/3867
摘要： Methods and apparatus are provided for implementing an efficient processor having state information included in each register. A processor has registers configured to hold both data and state information, such as carry and overflow information. State information and data can be read and written in the same operation. Holding state information along with data in the same register can provide a variety of benefits, particularly in the context of multithreaded programmable chips.
摘要翻译：提供了用于实现具有包括在每个寄存器中的状态信息的有效处理器的方法和装置。处理器具有被配置为保持数据和状态信息（诸如进位和溢出信息）的寄存器。状态信息和数据可以在相同的操作中进行读写。保持状态信息以及同一寄存器中的数据可以提供各种好处，特别是在多线程可编程芯片的上下文中。

39. 发明授权

US07162591B1 Processor memory having a dedicated port 有权
标题翻译：具有专用端口的处理器存储器
公开(公告)号：US07162591B1
公开(公告)日：2007-01-09
申请号：US10753052
申请日：2004-01-06
申请人： Tracy Miranda , Steven Perry
发明人： Tracy Miranda , Steven Perry
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1663 , G06F13/1647
摘要： Methods and apparatus are provided for closely coupling a dedicated memory port to a processor core while allowing external components access to the dedicated memory. A processor core such as a processor core on a programmable chip is provided with dedicated read access to a dual ported memory. Write access is arbitrated between processor core write access and read/write access by external components. A dedicated memory port is particularly beneficial in digital signal processing applications.
摘要翻译：提供了用于将专用存储器端口紧密耦合到处理器核心的同时允许外部组件访问专用存储器的方法和装置。诸如可编程芯片上的处理器核心的处理器核心被提供有对双端口存储器的专用读取访问。处理器核心写入访问和外部组件的读/写访问之间的写访问权限被仲裁。专用存储器端口在数字信号处理应用中是特别有益的。

40. 发明授权

US07058534B1 Method and apparatus for application specific test of PLDs 失效
标题翻译： PLD应用特异性检测方法和装置
公开(公告)号：US07058534B1
公开(公告)日：2006-06-06
申请号：US10394486
申请日：2003-03-19
申请人： Paul Tracy , Michael Harms , Jayabrata Ghosh Dastidar , Steven Perry
发明人： Paul Tracy , Michael Harms , Jayabrata Ghosh Dastidar , Steven Perry
IPC分类号： G01R31/00
CPC分类号： G01R31/318516
摘要： Method and apparatus for application specific testing of PLDs. The PLD has a number of resources, less than all of which are used for implementing a customer application. The method includes the following steps. The set of resources that is used for implementing the customer application is identified. A test is then performed only on the set and a test result is generated. Defective resources may be replaced. The PLD is identified as defective only if one of the resources associated with the customer application is defective. Such application specific testing allows the ability of the customer to perform in-system testing, the reduction of the time required for testing the PLD, and the testing of PLDs based on knowledge of the customer's application, among other advantages.
摘要翻译： PLD应用特定测试方法和设备。 PLD具有多个资源，少于用于实施客户应用程序的资源。该方法包括以下步骤。识别用于实现客户应用程序的一组资源。然后仅对集合进行测试，并生成测试结果。资源不足可能会被替换。只有当与客户应用程序相关联的资源之一有缺陷时，PLD才被识别为有缺陷。这样的应用程序特定测试允许客户执行系统测试，减少测试PLD所需的时间以及基于客户应用知识的PLD测试的能力等。

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