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31. 发明授权

US08982625B2 Memory program disturb reduction 有权
标题翻译：存储器程序干扰减少
公开(公告)号：US08982625B2
公开(公告)日：2015-03-17
申请号：US13600623
申请日：2012-08-31
申请人： Akira Goda , Mark Helm , Pranav Kalavade , Charan Srinivasan
发明人： Akira Goda , Mark Helm , Pranav Kalavade , Charan Srinivasan
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3454 , G11C16/3459
摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.
摘要翻译：一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。一种这样的方法可以包括在编程的第一次通过期间将第一偏置电压值应用于源极选择栅极以将存储器单元与源极隔离，在第一次处理期间将编程电压施加到存储器单元的页面的访问线编程的通过，以及在源选择栅极施加第二偏置电压值以在第二次编程期间隔离存储器单元与源极。公开了其它装置，系统和方法。

32. 发明申请

US20110063919A1 MEMORY KINK CHECKING 有权
标题翻译：内存闪烁检查
公开(公告)号：US20110063919A1
公开(公告)日：2011-03-17
申请号：US12559275
申请日：2009-09-14
申请人： Uday Chandrasekhar , Mark Helm
发明人： Uday Chandrasekhar , Mark Helm
IPC分类号： G11C16/04 , G11C29/00
CPC分类号： G11C16/3427 , G11C16/04 , G11C16/10 , G11C16/3454
摘要： This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
摘要翻译：本公开涉及内存扭结检查。一个实施例包括根据第一存储器单元的编程状态来选择性地将多个电压中的一个施加到第一数据线，其中第一存储器单元耦合到第一数据线和所选择的存取线。至少部分地由于施加到第一数据线的电压和至少第一数据线和第二数据线之间的电容耦合而确定对第二数据线的影响，其中第二数据线耦合到第二存储器单元，第二存储器单元与第一存储器单元相邻，并且第二存储器单元耦合到所选择的存取线。响应于所确定的效果，在施加到第二存储器单元的后续编程脉冲期间，将扭结校正应用于第二数据线。

33. 发明申请

US20110006372A1 FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES 有权
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US20110006372A1
公开(公告)日：2011-01-13
申请号：US12834231
申请日：2010-07-12
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

34. 发明申请

US20090003061A1 Select gate transistors and methods of operating the same 有权
标题翻译：选择栅极晶体管及其操作方法
公开(公告)号：US20090003061A1
公开(公告)日：2009-01-01
申请号：US11823547
申请日：2007-06-28
申请人： Mark Helm
发明人： Mark Helm
IPC分类号： G11C11/34
CPC分类号： G11C16/0483
摘要： Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of rows and columns, wherein each column comprises a string of the plurality of transistors coupled in series. Each such transistor includes a floating gate, a control gate, and a dielectric disposed between the floating gate and the control gate. Such a memory array also includes a plurality of select gates, wherein each select gate is coupled to each of the plurality of columns and each select gate includes a floating gate, a control gate, and an inter-gate dielectric layer. Each select gate of such a memory array also includes a switch electrically coupled between the floating gate and the control gate of the select gate and configured to switchably couple the floating gate and control gate of the select gate.
摘要翻译：公开了存储器阵列，方法和单元，例如涉及具有以多个行和列排列的多个晶体管的浮动栅极存储器阵列的那些，其中每列包括串联耦合的多个晶体管的串。每个这样的晶体管包括浮置栅极，控制栅极和布置在浮置栅极和控制栅极之间的电介质。这种存储器阵列还包括多个选择栅极，其中每个选择栅极耦合到多个列中的每一个，并且每个选择栅极包括浮置栅极，控制栅极和栅极间电介质层。这种存储器阵列的每个选择栅极还包括电耦合在选择栅极的浮动栅极和控制栅极之间的开关，并且被配置为可切换地耦合选择栅极的浮置栅极和控制栅极。

35. 发明申请

US20080042216A1 FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES 失效
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US20080042216A1
公开(公告)日：2008-02-21
申请号：US11877744
申请日：2007-10-24
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/70 , H01L29/94
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

36. 发明授权

US07279710B2 Structure and method of fabricating a transistor having a trench gate 有权
标题翻译：制造具有沟槽栅极的晶体管的结构和方法
公开(公告)号：US07279710B2
公开(公告)日：2007-10-09
申请号：US11231090
申请日：2005-09-20
申请人： Michael Smith , Mark Helm , Kirk Prall
发明人： Michael Smith , Mark Helm , Kirk Prall
IPC分类号： H01L29/10
CPC分类号： H01L29/66621 , H01L21/76224
摘要： An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation.
摘要翻译：制造具有非导电侧壁的沟槽栅极的集成电路晶体管。晶体管由填充有非导电材料的隔离沟道围绕。栅极沟槽的侧壁由非导电材料形成，并且基本上没有未蚀刻的衬底材料。结果，栅极沟槽的侧壁在晶体管的源极和漏极之间不形成不期望的导电路径，从而有利地减少在工作期间在源极和漏极之间流动的寄生电流的量。

37. 发明授权

US07265012B2 Formation of standard voltage threshold and low voltage threshold MOSFET devices 有权
公开(公告)号：US07265012B2
公开(公告)日：2007-09-04
申请号：US11216632
申请日：2005-08-31
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/8236 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

38. 发明申请

US20070093017A1 FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES 失效
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US20070093017A1
公开(公告)日：2007-04-26
申请号：US11566355
申请日：2006-12-04
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

39. 发明申请

US20050266678A1 Source lines for NAND memory devices 有权
标题翻译： NAND存储器件的源极线
公开(公告)号：US20050266678A1
公开(公告)日：2005-12-01
申请号：US10855844
申请日：2004-05-27
申请人： Mark Helm , Roger Lindsay
发明人： Mark Helm , Roger Lindsay
IPC分类号： G11C16/04 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/8238 , H01L21/8247 , H01L27/115 , H01L29/00
CPC分类号： H01L27/11524 , G11C16/0483 , H01L21/76895 , H01L27/115 , H01L27/11521
摘要： Methods and apparatus are provided. A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more columns of serially-connected floating-gate transistors. The source line also includes a second conductive layer formed on the first conductive layer, where the second layer has a greater electrical conductivity than the first conductive layer.
摘要翻译：提供了方法和装置。 NAND存储器件具有连接到两个或更多个串联连接的浮栅晶体管的源极线。源极线包括形成在衬底上并耦合到与两个或更多个串联连接的浮栅晶体管的列相关联的源极选择栅极的第一导电层。源极线还包括形成在第一导电层上的第二导电层，其中第二层具有比第一导电层更大的导电性。

40. 发明申请

US20050227427A1 Formation of standard voltage threshold and low voltage threshold MOSFET devices 有权
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US20050227427A1
公开(公告)日：2005-10-13
申请号：US11146812
申请日：2005-06-07
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

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