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31. 发明申请

US20110296431A1 METHOD AND APPARATUS FOR EFFICIENT HELPER THREAD STATE INITIALIZATION USING INTER-THREAD REGISTER COPY 有权
标题翻译：使用内部线程寄存器复制的有效帮助螺纹状态初始化的方法和装置
公开(公告)号：US20110296431A1
公开(公告)日：2011-12-01
申请号：US12787128
申请日：2010-05-25
申请人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
发明人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
IPC分类号： G06F9/46
CPC分类号： G06F9/544
摘要： This disclosure describes a method and system that may enable fast, hardware-assisted, producer-consumer style communication of values between threads. The method, in one aspect, uses a dedicated hardware buffer as an intermediary storage for transferring values from registers in one thread to registers in another thread. The method may provide a generic, programmable solution that can transfer any subset of register values between threads in any given order, where the source and target registers may or may not be correlated. The method also may allow for determinate access times, since it completely bypasses the memory hierarchy. Also, the method is designed to be lightweight, focusing on communication, and keeping synchronization facilities orthogonal to the communication mechanism. It may be used by a helper thread that performs data prefetching for an application thread, for example, to initialize the upward-exposed reads in the address computation slice of the helper thread code.
摘要翻译：本公开描述了一种方法和系统，其可以实现线程之间的值的快速，硬件辅助，生产者 - 消费者风格的通信。该方法在一个方面中使用专用硬件缓冲器作为用于将值从一个线程中的寄存器传送到另一线程中的寄存器的中间存储器。该方法可以提供通用的可编程解决方案，其可以以任何给定的顺序在线程之间传送寄存器值的任何子集，其中源寄存器和目标寄存器可以或可以不相关。该方法还可以允许确定的访问时间，因为它完全绕过存储器层次结构。此外，该方法被设计为轻量级，专注于通信，并保持与通信机制正交的同步设备。它可以由对应用程序线程执行数据预取的辅助线程使用，例如，初始化辅助线程代码的地址计算切片中的向上暴露的读取。

32. 发明申请

US20080263280A1 LOW COMPLEXITY SPECULATIVE MULTITHREADING SYSTEM BASED ON UNMODIFIED MICROPROCESSOR CORE 有权
标题翻译：基于未修改的微处理器核心的低复杂度测量多路复用系统
公开(公告)号：US20080263280A1
公开(公告)日：2008-10-23
申请号：US12147914
申请日：2008-06-27
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/3828 , G06F9/3842 , G06F9/3851 , G06F12/0815 , G06F2212/507
摘要： A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持线程级推测性执行的系统，方法和计算机程序产品，该处理单元适于以推测和非推测模式并行执行线程。每个处理单元包括与其可操作地连接的高速缓存的高速缓冲存储器层级。该装置包括仅在线程级推测模式中使用的每个处理单元本地的附加高速缓存级别，每个附加高速缓存用于存储推测结果以及处理推测性线程时与其相关联的处理器相关联的状态。在每个处理单元处的附加本地高速缓存级别互连，使得推测值和控制数据可以在并行执行线程之间转发。提供了一种控制实现，其实现在计算环境中执行的推测线程之间的推测性一致性。

33. 发明申请

US20080046700A1 Method and apparatus for efficient performance monitoring of a large number of simultaneous events 失效
公开(公告)号：US20080046700A1
公开(公告)日：2008-02-21
申请号：US11507307
申请日：2006-08-21
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , Y02D10/34
摘要： A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value. A data transfer sub-system additionally enables one or more of: read access or write access to both the count values in the first and second counter portions over a narrow bus, the read/write access for purposes of initializing and determining status of the count values for a monitored event type in response to a processor device request.

34. 发明授权

US09690583B2 Exploiting an architected list-use operand indication in a computer system operand resource pool 有权
公开(公告)号：US09690583B2
公开(公告)日：2017-06-27
申请号：US13251519
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30072 , G06F9/30138 , G06F9/3832 , G06F9/384 , G06F9/3859
摘要： A pool of available physical registers are provided for architected registers, wherein operations are performed that activate and deactivate selected architected registers, such that the deactivated selected architected registers need not retain values, and physical registers can be deallocated to the pool, wherein deallocation of physical registers is performed after a last-use by a designated last-use instruction, wherein the last-use information is provided either by the last-use instruction or a prefix instruction, wherein reads to deallocated architecture registers return an architected default value.

35. 发明授权

US09513915B2 Instruction merging optimization 有权
标题翻译：指令合并优化
公开(公告)号：US09513915B2
公开(公告)日：2016-12-06
申请号：US13432537
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： A computer system for optimizing instructions includes a processor including an instruction execution unit configured to execute instructions and an instruction optimization unit configured to optimize instructions and memory to store machine instructions to be executed by the instruction execution unit. The computer system is configured to perform a method including analyzing machine instructions from among a stream of instructions to be executed by the instruction execution unit, the machine instructions including a memory load instruction and a data processing instruction to perform a data processing function based on the memory load instruction, identifying the machine instructions as being eligible for optimization, merging the machine instructions into a single optimized internal instruction, and executing the single optimized internal instruction to perform a memory load function and a data processing function corresponding to the memory load instruction and the data processing instruction.
摘要翻译：用于优化指令的计算机系统包括：处理器，包括被配置为执行指令的指令执行单元和被配置为优化指令和存储器以存储由指令执行单元执行的机器指令的指令优化单元。计算机系统被配置为执行一种方法，包括从由指令执行单元执行的指令流中分析机器指令，包括存储器加载指令的机器指令和数据处理指令，以执行基于存储器加载指令，将机器指令识别为符合优化的要求，将机器指令合并到单个优化的内部指令中，以及执行单个优化内部指令以执行对应于存储器加载指令的存储器加载功能和数据处理功能，以及数据处理指令。

36. 发明授权

US09323530B2 Caching optimized internal instructions in loop buffer 有权
公开(公告)号：US09323530B2
公开(公告)日：2016-04-26
申请号：US13432512
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/3017 , G06F9/381 , G06F9/384
摘要： Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be executed, detecting a beginning of a first instruction loop in the instructions, determining that a first internal instruction loop corresponding to the first instruction loop is not stored in the loop buffer, fetching the first instruction loop, optimizing one or more instructions corresponding to the first instruction loop to generate a first optimized internal instruction loop, and storing the first optimized internal instruction loop in the loop buffer based on the determination that the first internal instruction loop is not stored in the loop buffer.

37. 发明授权

US08984042B2 Mixed precision estimate instruction computing narrow precision result for wide precision inputs 有权
公开(公告)号：US08984042B2
公开(公告)日：2015-03-17
申请号：US13369470
申请日：2012-02-09
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F7/38 , G06F7/00 , G06F15/00 , G06F7/483 , G06F7/499
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49905
摘要： A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value.

38. 发明授权

US08468531B2 Method and apparatus for efficient inter-thread synchronization for helper threads 有权
标题翻译：帮助线程有效的线程间同步的方法和设备
公开(公告)号：US08468531B2
公开(公告)日：2013-06-18
申请号：US12787810
申请日：2010-05-26
申请人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
发明人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/4881 , G06F9/5022 , G06F9/52 , G06F9/542
摘要： A monitor bit per hardware thread in a memory location may be allocated, in a multiprocessing computer system having a plurality of hardware threads, the plurality of hardware threads sharing the memory location, and each of the allocated monitor bit corresponding to one of the plurality of hardware threads. A condition bit may be allocated for each of the plurality of hardware threads, the condition bit being allocated in each context of the plurality of hardware threads. In response to detecting the memory location being accessed, it is determined whether a monitor bit corresponding to a hardware thread in the memory location is set. In response to determining that the monitor bit corresponding to a hardware thread is set in the memory location, a condition bit corresponding to a thread accessing the memory location is set in the hardware thread's context.
摘要翻译：可以在具有多个硬件线程的多处理计算机系统中分配存储器位置中的每个硬件线程的监视器位，所述多个硬件线程共享存储器位置，并且所分配的监视器位中的每一个对应于多个硬件线程。可以为多个硬件线程中的每一个分配条件位，该条件位在多个硬件线程的每个上下文中被分配。响应于检测到被访问的存储器位置，确定是否设置了与存储器位置中的硬件线程相对应的监视位。响应于确定对应于硬件线程的监视位设置在存储器位置中，在硬件线程的上下文中设置与访问存储位置的线程相对应的条件位。

39. 发明授权

US08453161B2 Method and apparatus for efficient helper thread state initialization using inter-thread register copy 有权
标题翻译：使用线程间寄存器复制的有效帮助线程状态初始化的方法和装置
公开(公告)号：US08453161B2
公开(公告)日：2013-05-28
申请号：US12787128
申请日：2010-05-25
申请人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
发明人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
IPC分类号： G06F13/00 , G06F12/00 , G06F9/30
CPC分类号： G06F9/544
摘要： This disclosure describes a method and system that may enable fast, hardware-assisted, producer-consumer style communication of values between threads. The method, in one aspect, uses a dedicated hardware buffer as an intermediary storage for transferring values from registers in one thread to registers in another thread. The method may provide a generic, programmable solution that can transfer any subset of register values between threads in any given order, where the source and target registers may or may not be correlated. The method also may allow for determinate access times, since it completely bypasses the memory hierarchy. Also, the method is designed to be lightweight, focusing on communication, and keeping synchronization facilities orthogonal to the communication mechanism. It may be used by a helper thread that performs data prefetching for an application thread, for example, to initialize the upward-exposed reads in the address computation slice of the helper thread code.
摘要翻译：本公开描述了一种方法和系统，其可以实现线程之间的值的快速，硬件辅助，生产者 - 消费者风格的通信。该方法在一个方面中使用专用硬件缓冲器作为用于将值从一个线程中的寄存器传送到另一线程中的寄存器的中间存储器。该方法可以提供通用的可编程解决方案，其可以以任何给定的顺序在线程之间传送寄存器值的任何子集，其中源寄存器和目标寄存器可以或可以不相关。该方法还可以允许确定的访问时间，因为它完全绕过存储器层次结构。此外，该方法被设计为轻量级，专注于通信，并保持与通信机制正交的同步设备。它可以由对应用程序线程执行数据预取的辅助线程使用，例如，初始化辅助线程代码的地址计算切片中的向上暴露的读取。

40. 发明申请

US20130086364A1 Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand Last-User Information 审中-公开
标题翻译：基于具有操作数最后用户信息的建筑计算机指令集管理寄存器缓存
公开(公告)号：US20130086364A1
公开(公告)日：2013-04-04
申请号：US13251505
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30138 , G06F9/3832 , G06F9/384 , G06F9/3859
摘要： A multi-level register hierarchy is disclosed comprising a first level pool of registers for caching registers of a second level pool of registers in a system wherein programs can dynamically release and re-enable architected registers such that released architected registers need not be maintained by the processor, the processor accessing operands from the first level pool of registers, wherein a last-use instruction is identified as having a last use of an architected register before being released, the last-use architected register being released causes the multi-level register hierarchy to discard any correspondence of an entry to said last use architected register.
摘要翻译：公开了一种多级寄存器层级，其包括用于缓存系统中第二级寄存器池的寄存器的第一级寄存器池，其中程序可以动态地释放并重新启用架构化寄存器，使得发布的架构寄存器不需要由处理器，处理器从第一级寄存器池访问操作数，其中最后使用指令被识别为在被释放之前最后使用架构化寄存器，最后使用的结构化寄存器被释放导致多级寄存器层级丢弃对上一次使用的结构化寄存器的条目的任何通信。

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