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    • 31. 发明申请
    • MODEL-BASED SYSTEMS AND METHODS FOR MONITORING RESOURCES
    • 基于模型的系统和监测资源的方法
    • US20120221314A1
    • 2012-08-30
    • US13465708
    • 2012-05-07
    • Dmitri BourlatchkovBrendan BehanYu LiNils MeierLeo PecherskyStephen P. RosenbergGeoff Vona
    • Dmitri BourlatchkovBrendan BehanYu LiNils MeierLeo PecherskyStephen P. RosenbergGeoff Vona
    • G06F9/44
    • G06F11/3409
    • Modeling systems and methods for constructing one or more models of a computing system using collected data. Certain model-based systems build topology models and/or model instances by transforming collected performance data into a collection-location independent form. In certain examples, systems include at least one agent for collecting performance data from monitored resource(s), canonical data transform (CDT) configurations, and a data transformation module for performing data transform operation(s) on the performance data based on at least one CDT configuration. The data transform operation may include generating and/or updating a topology model, assigning metrics to model object(s), updating properties of model object(s), creating associations between existing model objects, or the like. Certain systems and methods also allow for a single piece of data to be processed by multiple models or for pieces of data collected from different locations to be matched and/or associated with the same model object.
    • 使用收集的数据构建计算系统的一个或多个模型的建模系统和方法。 某些基于模型的系统通过将收集的性能数据转换为与集合位置无关的形式来构建拓扑模型和/或模型实例。 在某些示例中,系统包括至少一个代理,用于从所监视的资源,规范数据变换(CDT)配置收集性能数据,以及用于至少基于演示数据执行数据变换操作的数据变换模块 一个CDT配置。 数据变换操作可以包括生成和/或更新拓扑模型,向模型对象分配度量,更新模型对象的属性,创建现有模型对象之间的关联等。 某些系统和方法还允许单个数据由多个模型或从不同位置收集的数据进行处理以与同一模型对象匹配和/或关联。
    • 33. 发明授权
    • FPGA and method and system for configuring and debugging a FPGA
    • FPGA以及配置和调试FPGA的方法和系统
    • US07882465B2
    • 2011-02-01
    • US11944408
    • 2007-11-21
    • Yu LiGuo Hui LinQiang LiuYu Dong Yang
    • Yu LiGuo Hui LinQiang LiuYu Dong Yang
    • G06F17/50H04B1/38H03K19/173G01R31/28
    • G01R31/31705G01R31/318519
    • The present invention provides a Field Programmable Gate Array (FPGA), a system for debugging a Field Programmable Gate Array, a method for debugging a Field Programmable Gate Array, a FPGA configuration data product and a method and system for configuring a FPGA. According to one aspect of the invention, there is provided a Field Programmable Gate Array (FPGA) having a logic unit under test and comprising: a probe signal selecting unit configured to select at least one probe point from a plurality of probe points in said logic unit under test, and obtain a probe signal at said probe point; and a high speed serial transceiver configured to convert said probe signal into a high speed serial signal and transmit it to outside.
    • 本发明提供了现场可编程门阵列(FPGA),用于调试现场可编程门阵列的系统,用于调试现场可编程门阵列的方法,FPGA配置数据产品以及用于配置FPGA的方法和系统。 根据本发明的一个方面,提供了一种具有被测逻辑单元的现场可编程门阵列(FPGA),包括:探测信号选择单元,被配置为从所述逻辑中的多个探测点中选择至少一个探测点 并在所述探测点获取探测信号; 以及配置成将所述探测信号转换为高速串行信号并将其传输到外部的高速串行收发器。
    • 36. 发明申请
    • Memory card connector
    • 存储卡连接器
    • US20100041260A1
    • 2010-02-18
    • US12222616
    • 2008-08-13
    • Ming Chun LaiYu Li
    • Ming Chun LaiYu Li
    • H01R13/62
    • H01R13/635
    • A memory card connector adapted for accommodating a memory card includes a dielectric housing, a plurality of terminals received in the dielectric housing, a primary ejector and a secondary ejector. The dielectric housing defines a recess for accommodating the memory card. The primary ejector is received in one lateral side of the dielectric housing for ejecting the memory card out of the dielectric housing. The secondary ejector is received in the other lateral side of the dielectric housing for cooperating with the primary ejector to push the memory card out of the dielectric housing. After the memory card is fully inserted in the recess, the primary ejector stores an elastic force therein but is controlled to provide a substantially zero pushing force to the memory card. At the same time, the secondary ejector is still elastically urged against the memory card by an elastic force stored therein.
    • 适于容纳存储卡的存储卡连接器包括绝缘壳体,容纳在电介质壳体中的多个端子,初级喷射器和次级喷射器。 绝缘壳体限定用于容纳存储卡的凹部。 主推出器被容纳在电介质外壳的一个侧面中,用于将存储卡从电介质外壳中排出。 辅助喷射器被容纳在电介质壳体的另一个侧面中,用于与主喷射器协作以将存储卡推出介质壳体。 在存储卡完全插入凹槽中之后,主喷射器在其中存储弹性力,但是被控制以向存储卡提供基本为零的推力。 同时,二次喷射器通过存储在其中的弹性力仍然弹性地推靠在存储卡上。
    • 37. 发明授权
    • Electrical connector and method of manufacturing the same
    • 电连接器及其制造方法
    • US07632153B1
    • 2009-12-15
    • US12184540
    • 2008-08-01
    • Ming-Chun LaiYu Li
    • Ming-Chun LaiYu Li
    • H01R33/00H05K3/30
    • H01R13/405H01R43/24Y10T29/4922
    • An electrical connector includes a dielectric housing and a plurality of electrical terminals integrated with the dielectric housing. A top of the dielectric housing defines a plurality of locating slots. A bottom of each locating slot defines a manufacturing hole. Each electrical terminal has a plate-shaped fixing portion embedded in the dielectric housing. A connecting end extends from one end of the fixing portion and out of the dielectric housing. A bending portion is bent upward from the other end of the fixing portion, and a contact portion obliquely extends from a top end of the bending portion. The fixing portion defines a fixing hole therein with respect to the contact portion. The fixing hole is located corresponding to and communicating with the manufacturing hole. The contact portion is received in the locating slot and covers the manufacturing hole.
    • 电连接器包括绝缘壳体和与绝缘壳体集成的多个电端子。 绝缘壳体的顶部限定多个定位槽。 每个定位槽的底部限定一个制造孔。 每个电端子具有嵌入在绝缘壳体中的板状固定部分。 连接端从固定部分的一端延伸出绝缘外壳。 弯曲部分从固定部分的另一端向上弯曲,并且接触部分从弯曲部分的顶端倾斜延伸。 固定部分在其中限定了相对于接触部分的固定孔。 固定孔对应于并与制造孔连通。 接触部分被容纳在定位槽中并覆盖制造孔。
    • 38. 发明申请
    • Metal Oxide Semiconductor Device and Method for Manufacturing the Same
    • 金属氧化物半导体器件及其制造方法
    • US20090294875A1
    • 2009-12-03
    • US12536005
    • 2009-08-05
    • Haohua YeHok Min HoYu Li
    • Haohua YeHok Min HoYu Li
    • H01L29/78
    • H01L21/26506H01L21/26513H01L29/665H01L29/6659H01L29/78621
    • A Metal Oxide Semiconductor device includes a semiconductor substrate; a gate electrode formed on the surface of the substrate, having an offset spacer on each side; source/drain electrodes in the substrate having lightly doped regions respectively; metal silicide located on the gate electrode and the source/drain electrodes; and first impurity ions and second impurity ions in the lightly doped regions. A method for manufacturing a Metal Oxide Semiconductor device includes forming a gate electrode on a semiconductor substrate; implanting first impurity ions and second impurity ions to form lightly doped regions; depositing a dielectric layer and etching the dielectric layer to form offset spacers; implanting the first impurity ions to form the source/drain electrodes; forming metal silicide on the surfaces of the gate electrode and the source/drain regions. This invention can effectively prevent metal nickel diffusion into the lightly doped regions.
    • 金属氧化物半导体器件包括半导体衬底; 形成在所述基板的表面上的栅电极,在每一侧具有偏移间隔物; 分别具有轻掺杂区的衬底中的源/漏电极; 位于栅电极和源/漏电极上的金属硅化物; 以及轻掺杂区域中的第一杂质离子和第二杂质离子。 金属氧化物半导体器件的制造方法包括在半导体衬底上形成栅电极; 注入第一杂质离子和第二杂质离子以形成轻掺杂区域; 沉积电介质层并蚀刻介电层以形成偏移间隔物; 注入第一杂质离子以形成源极/漏极; 在栅极电极和源极/漏极区域的表面上形成金属硅化物。 本发明可有效地防止金属镍扩散入轻掺杂区域。
    • 39. 发明授权
    • Socket connector
    • 插座连接器
    • US07581993B1
    • 2009-09-01
    • US12081957
    • 2008-04-24
    • Ming-Chun LaiYu Li
    • Ming-Chun LaiYu Li
    • H01R13/502
    • H01R12/57H01R12/7047H01R13/2442
    • The present invention provides a socket connector adapted for a charger capable of charging a bluetooth earphone. The socket connector includes a plurality of terminals and a dielectric body. Each of the terminals has a soldering portion. All the soldering portions are connected with a terminal strip so that all the terminals are integrated. The dielectric body is integrally formed with the integrated terminals that are prearranged in a mold by injection molding. The soldering portions and the terminal strip extend out of the dielectric body so that the terminal strip can be removed after the terminals and the dielectric body are fixed together.
    • 本发明提供了适用于能够对蓝牙耳机充电的插座连接器。 插座连接器包括多个端子和电介质体。 每个端子具有焊接部分。 所有焊接部分都与端子板连接,使得所有的端子都被集成。 电介质体与通过注射成型在模具中预先布置的集成端子一体形成。 焊接部分和端子条从电介质体延伸出来,使得在端子和电介质体固定在一起之后可以去除端子条。
    • 40. 发明申请
    • Method and apparatus for reconstruction of an image in image space using basis functions (RIB) for partially parallel imaging
    • 用于使用用于部分并行成像的基函数(RIB)来重建图像空间中的图像的方法和装置
    • US20080278165A1
    • 2008-11-13
    • US12148367
    • 2008-04-18
    • Yu LiFeng HuangG. Randy Duensing
    • Yu LiFeng HuangG. Randy Duensing
    • G01R33/48
    • G01R33/5611
    • Embodiments of the invention pertain to a method and apparatus for image reconstruction for parallel Magnetic Resonance Imaging (MRI). In a specific embodiment, a method for image reconstruction in image space is provided. The method can suppress aliasing caused by undersampling when the number of sampling lines in k-space is reduced to increase the imaging speed. In an embodiment, suppressing aliasing from under-sampling can improve the quality of images reconstructed from the data acquired using a MRI coil array. In an embodiment, the method operates in image space and achieves a good resolution. In the reconstruction, the sum of square errors can be minimized within a region of interest, which can allow the image reconstruction to be optimized in a particular imaging region of interest by sacrificing the reconstruction of other regions. In a further embodiment, image reconstruction can be implemented region by region, allowing global optimization by spending a longer time in reconstruction.
    • 本发明的实施例涉及用于并行磁共振成像(MRI)的图像重建的方法和装置。 在具体实施例中,提供了一种用于图像空间中的图像重建的方法。 当减小k空间中的采样线的数量以增加成像速度时,该方法可以抑制由欠采样引起的混叠。 在一个实施例中,抑制来自欠采样的混叠可以改善从使用MRI线圈阵列获取的数据重建的图像的质量。 在一个实施例中,该方法在图像空间中操作并且实现良好的分辨率。 在重建中,平方误差的和可以在感兴趣的区域内最小化,这可以允许通过牺牲其他区域的重建来在特定的感兴趣的成像区域中优化图像重建。 在另一个实施例中,图像重建可以逐个区域实现,从而通过在重建中花更长的时间来实现全局优化。