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31. 发明授权

US08326904B2 Trigonometric summation vector execution unit 失效
标题翻译：三角求和向量执行单元
公开(公告)号：US08326904B2
公开(公告)日：2012-12-04
申请号：US12360243
申请日：2009-01-27
申请人： Adam J. Muff , Matthew R. Tubbs
发明人： Adam J. Muff , Matthew R. Tubbs
IPC分类号： G06F1/02
CPC分类号： G06F7/485 , G06F7/49936 , G06F7/509 , G06F7/5443 , G06F7/548 , G06F9/30014 , G06F2207/3828
摘要： A unique instruction and exponent adjustment adder selectively shift outputs from multiple execution units, including a plurality of multipliers, in a processor core in order to scale mantissas for related trigonometric functions used in a vector dot product.
摘要翻译：独特的指令和指数调整加法器在处理器核心中选择性地将来自多个执行单元（包括多个乘法器）的输出移位，以缩放用于矢量点积中的相关三角函数的尾数。

32. 发明申请

US20110298788A1 PERFORMING VECTOR MULTIPLICATION 有权
标题翻译：执行矢量多项式
公开(公告)号：US20110298788A1
公开(公告)日：2011-12-08
申请号：US12794207
申请日：2010-06-04
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06F7/483 , G06F7/5443
摘要： A method includes receiving packed data corresponding to pixel components to be processed at a graphics pipeline. The method includes unpacking the packed data to generate floating point numbers that correspond to the pixel components. The method also includes routing each of the floating point numbers to a separate lane of the graphics pipeline. Each of the floating point numbers are to be processed by multiplier units of the graphics pipeline.
摘要翻译：一种方法包括在图形流水线处接收对应于要处理的像素分量的打包数据。该方法包括打包打包数据以产生对应于像素分量的浮点数。该方法还包括将每个浮点数路由到图形流水线的单独通道。每个浮点数由图形管线的乘法器单元处理。

33. 发明授权

US08412980B2 Fault tolerant stability critical execution checking using redundant execution pipelines 失效
标题翻译：使用冗余执行管道的容错稳定性关键执行检查
公开(公告)号：US08412980B2
公开(公告)日：2013-04-02
申请号：US12794256
申请日：2010-06-04
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F11/16 , G06F11/00
CPC分类号： G06F11/0751 , G06F9/30185 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F11/1641 , G06F2201/845
摘要： A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions.
摘要翻译：电路布置和方法利用处理单元中的现有冗余执行流水线并行执行稳定性关键指令的多个实例，从而可以比较指令的多个实例的结果以便检测错误。对于不需要或不需要容错或稳定性关键执行的其他类型的指令，以更传统的方式利用冗余执行流水线，使多个非稳定性关键指令同时发布到冗余执行管线并由其执行。因此，对于非稳定性关键程序代码，保留具有多个冗余执行单元的性能优点，但是在需要对某些程序代码进行容错或稳定性关键执行的情况下，冗余执行单元可以重新利用以提供对这种指令的无故障执行的更大保证。

34. 发明申请

US20110302450A1 FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDANT EXECUTION PIPELINES 失效
标题翻译：使用冗余执行管道的故障稳定性关键执行检查
公开(公告)号：US20110302450A1
公开(公告)日：2011-12-08
申请号：US12794256
申请日：2010-06-04
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F11/07 , G06F11/14
CPC分类号： G06F11/0751 , G06F9/30185 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F11/1641 , G06F2201/845
摘要： A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions.
摘要翻译：电路布置和方法利用处理单元中的现有冗余执行流水线并行执行稳定性关键指令的多个实例，从而可以比较指令的多个实例的结果以便检测错误。对于不需要或不需要容错或稳定性关键执行的其他类型的指令，以更传统的方式利用冗余执行流水线，使多个非稳定性关键指令同时发布到冗余执行管线并由其执行。因此，对于非稳定性关键程序代码，保留具有多个冗余执行单元的性能优点，但是在需要对某些程序代码进行容错或稳定性关键执行的情况下，冗余执行单元可以重新利用以提供对这种指令的无故障执行的更大保证。

35. 发明申请

US20090182990A1 Method and Apparatus for a Pipelined Multiple Operand Minimum and Maximum Function 有权
标题翻译：流水线多操作数最小和最大函数的方法和装置
公开(公告)号：US20090182990A1
公开(公告)日：2009-07-16
申请号：US12014183
申请日：2008-01-15
申请人： Adam J. Muff , Matthew R. Tubbs
发明人： Adam J. Muff , Matthew R. Tubbs
IPC分类号： G06F9/302
CPC分类号： G06F9/30021 , G06F7/22 , G06F7/49936 , G06F7/57 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30145 , G06F9/345
摘要： Embodiments of the invention provide methods and apparatus for executing a multiple operand minimum or maximum instructions. Executing the multiple operand minimum or maximum instruction comprises transferring more than two operands to one or more processing lanes of a vector unit. A first compare operation may be performed in at least one processing lane of the vector unit to determine a greater or smaller of a first operand and a second operand. The greater (or smaller) operand may be transferred to a dot product unit, wherein, in a second compare operation, the transferred operand is compared to at least a third operand to determine one of the greater and smaller of the more than two operands.
摘要翻译：本发明的实施例提供了用于执行多个操作数最小或最大指令的方法和装置。执行多操作数最小或最大指令包括将多于两个操作数传送到向量单元的一个或多个处理通道。可以在向量单元的至少一个处理通道中执行第一比较操作，以确定第一操作数和第二操作数的更大或更小。较大（或更小）的操作数可以被转移到点积单位，其中，在第二比较操作中，将传送的操作数与至少第三操作数进行比较，以确定多于两个操作数中的较大和较小的操作数之一。

36. 发明授权

US10261793B2 Instruction predication using instruction address pattern matching 有权
公开(公告)号：US10261793B2
公开(公告)日：2019-04-16
申请号：US13328185
申请日：2011-12-16
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/30
摘要： A particular method includes receiving, at a processor, an instruction and an address of the instruction. The method also includes preventing execution of the instruction based at least in part on determining that the address is within a range of addresses.

37. 发明授权

US09195463B2 Processing core with speculative register preprocessing in unused execution unit cycles 有权
标题翻译：在未使用的执行单位周期内处理具有推测寄存器预处理的内核
公开(公告)号：US09195463B2
公开(公告)日：2015-11-24
申请号：US13307575
申请日：2011-11-30
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/302 , G06F9/38 , G06F7/499 , G06F9/30
CPC分类号： G06F9/383 , G06F7/499 , G06F9/30014 , G06F9/30025 , G06F9/3836 , G06F9/384 , G06F9/3875 , G06F9/3885
摘要： A method and circuit arrangement speculatively preprocess data stored in a register file during otherwise unused cycles in an execution unit, e.g., to prenormalize denormal floating point values stored in a floating point register file, to decompress compressed values stored in a register file, to decrypt encrypted values stored in a register file, or to otherwise preprocess data that is stored in an unprocessed form in a register file.
摘要翻译：一种方法和电路装置在执行单元中的其他未使用的周期期间推测性地预处理存储在寄存器文件中的数据，例如，将存储在浮点寄存器文件中的非正常浮点值预正规化，以解压缩存储在寄存器堆中的压缩值，以解密存储在寄存器文件中的加密值，或以其他方式预处理以未处理形式存储在寄存器文件中的数据。

38. 发明授权

US09075599B2 Opcode space minimizing architecture utilizing a least significant portion of an instruction address as upper register address bits 有权
标题翻译：操作码空间最小化结构，利用指令地址的最低有效部分作为高位寄存器地址位
公开(公告)号：US09075599B2
公开(公告)日：2015-07-07
申请号：US12894697
申请日：2010-09-30
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/345 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30098 , G06F9/3016 , G06F9/30181 , G06F9/345 , G06F9/3824
摘要： Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the most significant side of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory.
摘要翻译：由于现代微处理器内核中的寄存器数量和新指令的数量不断增加，指令编码中存在的地址宽度不断扩大，更少的指令操作码可用，使得更难于将现有架构的新指令添加到现有的架构中，而无需使用不正当的具有诸如源破坏性操作等缺点的技巧。所公开的发明利用专门的解码和地址计算硬件，其将指令地址的固定数量的最低有效位连接到包含在指令中的每个寄存器地址部分的最高有效侧，从而产生完整寄存器地址，而不是提供完整寄存器指令中使用的每个寄存器的地址宽度。这释放了其他指令的有价值的操作码空间，避免了编译器的复杂性。这很好地与汇编语言中大多数循环展开的方式保持一致，独立操作在内存中彼此靠近。

39. 发明申请

US20100042813A1 Redundant Execution of Instructions in Multistage Execution Pipeline During Unused Execution Cycles 失效
标题翻译：在多个执行循环中执行多级执行管道中的指令冗余执行
公开(公告)号：US20100042813A1
公开(公告)日：2010-02-18
申请号：US12191331
申请日：2008-08-14
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3869
摘要： A pipelined execution unit uses the bubbles that occur during execution to selectively repeat operations performed in one or more stages of a multistage execution pipeline to verify the results of such operations during otherwise unused execution cycles for the execution pipeline. Whenever a bubble follows a particular instruction within an execution pipeline, the result of an operation that is performed for that instruction by a particular stage of the execution pipeline may be stored, and the operation may be repeated by the stage in a subsequent execution cycle in which no productive operation would otherwise be performed due to the presence of the bubble. The results of the operations may then be compared and used to either verify the original result or identify a potential error in the execution of the instruction.
摘要翻译：流水线执行单元使用在执行期间发生的气泡来选择性地重复在多级执行流水线的一个或多个阶段中执行的操作，以在执行流水线的另外未使用的执行周期期间验证这种操作的结果。每当气泡遵循执行流水线中的特定指令时，可以存储由执行流水线的特定阶段对该指令执行的操作的结果，并且可以在后续执行周期中的阶段重复该操作，否则由于存在气泡而不能进行生产操作。然后可以将操作的结果进行比较并用于验证原始结果或识别指令执行中的潜在错误。

40. 发明申请

US20100042812A1 Data Dependent Instruction Decode 有权
标题翻译：数据相关指令解码
公开(公告)号：US20100042812A1
公开(公告)日：2010-02-18
申请号：US12191337
申请日：2008-08-14
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/30181 , G06F9/3016
摘要： A circuit arrangement and method support data dependent instruction decoding, whereby instructions are decoded, in part, using decode data that is stored in operand registers identified by such instructions. An instruction may include an opcode and at least one operand that identifies a register. During execution of the instruction, the instruction is first decoded using the opcode, and then decode data stored in the operand register is retrieved and used to further decode the instruction, e.g., to select from among a plurality of operations or instruction types associated with the same opcode.
摘要翻译：一种电路装置和方法支持数据相关指令解码，其中部分地使用存储在由这些指令识别的操作数寄存器中的解码数据来解码指令。指令可以包括操作码和标识寄存器的至少一个操作数。在执行指令期间，首先使用操作码解码指令，然后检索存储在操作数寄存器中的解码数据，并用于进一步解码指令，例如，从多个操作或与该指令相关联的指令类型中进行选择相同的操作码

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