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31. 发明申请

US20100161058A1 Multiple-State Geometry Artificial Disc With Compliant Insert and Method 审中-公开
标题翻译：多状态几何人造盘与标准的插入和方法
公开(公告)号：US20100161058A1
公开(公告)日：2010-06-24
申请号：US12344212
申请日：2008-12-24
申请人： Mahmoud F. Abdelgany , Aaron D. Markworth , Young Hoon Oh
发明人： Mahmoud F. Abdelgany , Aaron D. Markworth , Young Hoon Oh
IPC分类号： A61F2/44
CPC分类号： A61F2/442 , A61F2002/30471 , A61F2002/30563 , A61F2002/30565 , A61F2002/30581 , A61F2002/30841 , A61F2220/0091 , A61F2310/00011 , A61F2310/00023
摘要： A multiple-state geometry artificial disc assembly attached to vertebrae includes a compliant load bearing spacer element having an upper curved portion and a lower curved portion, a first plate coupled on the upper curved portion of the compliant load bearing spacer element and a second plate coupled on the lower curved portion of the compliant load bearing spacer element. The first plate and the second plate preferably are of a flexible material. The first plate and the second plate transitions from a convex configuration to a concave configuration in-situ in a vertebral disc space. The upper curved portion and the lower curved portion of the compliant load bearing spacer element may include a plurality of openings. The compliant load bearing spacer element may further include a middle cylindrical portion dimensioned and configured to match a gap between the first plate and the second plate.
摘要翻译：附接到椎骨的多状态几何人造椎盘组件包括具有上弯曲部分和下弯曲部分的顺从承载间隔元件，联接在柔性承载间隔元件的上弯曲部分上的第一板和耦合在柔性负载隔离元件的下弯曲部分上。第一板和第二板优选为柔性材料。第一板和第二板在椎间盘空间中原位从凸形状转变为凹形构型。柔性负载隔离元件的上弯曲部分和下弯曲部分可以包括多个开口。柔性承载间隔元件还可以包括尺寸和构造成匹配第一板和第二板之间的间隙的中间圆柱形部分。

32. 发明申请

US20090115475A1 Semiconductor device and operating method thereof 失效
标题翻译：半导体器件及其操作方法
公开(公告)号：US20090115475A1
公开(公告)日：2009-05-07
申请号：US12217002
申请日：2008-06-30
申请人： Young-Hoon Oh
发明人： Young-Hoon Oh
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0812 , H03L7/093
摘要： A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.
摘要翻译：半导体器件的延迟锁定环（DLL）具有相对小的面积和低的电流消耗，同时具有校正占空比的功能。所述半导体器件包括分配单元，其被配置为接收和分离参考时钟以输出对应于所述参考时钟的第一边缘的第一时钟和对应于第二边缘的第二时钟;电压生成单元，被配置为生成对应于对应于第一时钟的占空比和对应于第二时钟的占空比的第二电压，电压比较单元，被配置为将第一和第二电压的电平彼此进行比较;以及时钟延迟单元，被配置为接收用于响应于电压比较单元的输出信号来确定延迟量的接收时钟的第一和第二时钟。

33. 发明授权

US07492645B2 Internal voltage generator for semiconductor memory device 有权
标题翻译：用于半导体存储器件的内部电压发生器
公开(公告)号：US07492645B2
公开(公告)日：2009-02-17
申请号：US11527440
申请日：2006-09-27
申请人： Khil-Ohk Kang , Young-Hoon Oh
发明人： Khil-Ohk Kang , Young-Hoon Oh
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/147
摘要： An internal voltage generator for a semiconductor memory device is provided. The internal voltage generator includes a first reference voltage generator for generating a first reference voltage, a second reference voltage generator for generating a second reference voltage, a core voltage generator for raising a core voltage based on the first reference voltage, and a core voltage discharger for discharging the core voltage depending on the second reference voltage.
摘要翻译：提供了一种用于半导体存储器件的内部电压发生器。内部电压发生器包括用于产生第一参考电压的第一参考电压发生器，用于产生第二参考电压的第二参考电压发生器，用于基于第一参考电压提高核心电压的核心电压发生器，以及核心电压放电器用于根据第二参考电压放电核心电压。

34. 发明授权

US06436960B1 Farnesyl transferase inhibitors having a piperidine structure and process for preparation thereof 失效
标题翻译：具有哌啶结构的法呢基转移酶抑制剂及其制备方法
公开(公告)号：US06436960B1
公开(公告)日：2002-08-20
申请号：US09601426
申请日：2000-08-01
申请人： You Seung Shin , Jong Sung Koh , Hyun Il Lee , Jin Ho Lee , Jong Hyun Kim , Hyun Ho Chung , Kwi Hwa Kim , Tae Hwan Kwak , Seong Gu Ro , In Ae Ahn , Tae Saeng Choi , Young Hoon Oh , Chung Mi Kim , Sun Hwa Lee , Hyun Sung Kim
发明人： You Seung Shin , Jong Sung Koh , Hyun Il Lee , Jin Ho Lee , Jong Hyun Kim , Hyun Ho Chung , Kwi Hwa Kim , Tae Hwan Kwak , Seong Gu Ro , In Ae Ahn , Tae Saeng Choi , Young Hoon Oh , Chung Mi Kim , Sun Hwa Lee , Hyun Sung Kim
IPC分类号： A61K31454
CPC分类号： C07D401/14 , C07D417/14
摘要： The present invention relates to a novel piperidine derivative represented by formula (1) which shows an inhibitory activity against farnesyl transferase or pharmaceutically acceptable salts thereof, in which A, E and G are defined in the specification; to a process for preparation of the compound of formula (1); to an intermediate which is used in the preparation of the compound of formula (1); and to a pharmaceutical composition comprising the compound of formula (1) as an active ingredient.
摘要翻译：本发明涉及式（1）所示的新型哌啶衍生物，其表现出对法呢基转移酶的抑制活性或其药学上可接受的盐，其中A，E和G在本说明书中定义; 涉及制备式（1）化合物的方法; 涉及用于制备式（1）化合物的中间体; 以及包含式（1）化合物作为活性成分的药物组合物。

35. 发明授权

US11071632B2 Intervertebral implant device 有权
公开(公告)号：US11071632B2
公开(公告)日：2021-07-27
申请号：US16840381
申请日：2020-04-04
申请人： Young Hoon Oh , Rachel Oh
发明人： Young Hoon Oh , Rachel Oh
IPC分类号： A61F2/44
摘要： An intervertebral implant device includes a first plate having a first fixation component; and a first set of outwardly extending projecting members. The device also includes a second plate having a second fixation component; and a second set of outwardly extending projecting members that compliment an alignment with the first set of outwardly extending projecting members. The device also includes a core member that extends through the first plate and the second plate. The core member limits movement of the first plate away from the second plate; and a connecting member that connects to the core member.

36. 发明授权

US08169847B2 Semiconductor memory apparatus and refresh control method of the same 有权
标题翻译：半导体存储装置及其刷新控制方法相同
公开(公告)号：US08169847B2
公开(公告)日：2012-05-01
申请号：US12494857
申请日：2009-06-30
申请人： Young Hoon Oh
发明人： Young Hoon Oh
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C2211/4016 , G11C2211/4065
摘要： A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a drain connected to a bit line, and a source connected to a source line. FBC transistor pairs are formed by sharing the source lines in the plurality of the floating body cell transistors. When a refresh signal is enabled, the semiconductor memory apparatus is configured to read data stored in the memory cell block by enabling a refresh read signal and then configured to rewrite the read data in the memory cell block by enabling a refresh write signal.
摘要翻译：提出了半导体存储装置和刷新控制方法。半导体存储装置包括由多个浮体单元（FBC）晶体管构成的存储单元块。每个FBC晶体管具有连接到字线的栅极，连接到位线的漏极和连接到源极线的源极。通过共享多个浮体单元晶体管中的源极线来形成FBC晶体管对。当启用刷新信号时，半导体存储装置被配置为通过启用刷新读取信号来读取存储在存储器单元块中的数据，然后通过启用刷新写信号来配置为重写存储单元块中的读取数据。

37. 发明申请

US20110009706A1 Adjustable Polyaxial Tissue Retractor 有权
标题翻译：可调多轴组织牵引器
公开(公告)号：US20110009706A1
公开(公告)日：2011-01-13
申请号：US12501990
申请日：2009-07-13
申请人： Mahmoud F. Abdelgany , Young Hoon Oh , Kevin Sichler
发明人： Mahmoud F. Abdelgany , Young Hoon Oh , Kevin Sichler
IPC分类号： A61B1/32
CPC分类号： A61B17/0293
摘要： An adjustable polyaxial tissue retractor includes a retraction bar including a plurality of etched teeth, a retraction blade coupled to the retraction bar, a connector including a quick release component cavity and an outwardly protruding and expandable round bulbous body, a quick release component engaged with at least one tooth of the retraction bar via a retraction bar cavity, where the quick release component is configured to loosely mate with the quick release component cavity, a saddle pin engaged within the connector via a first channel bored through the connector and contacting the bulbous body causing the bulbous body to outwardly expand, and a base including a plurality of embedded sockets and directly connected to the bulbous body, where the base receives the connector.
摘要翻译：可调节的多轴组织牵缩器包括一个包括多个蚀刻齿的收回杆，一个连接到收回杆的缩回刀片，一个连接器，包括一个快速释放部件空腔和一个向外伸出和可扩张的圆球形体，通过缩回杆腔的至少一个齿的收缩杆，其中快速释放部件构造成与快速释放部件空腔松散配合;鞍形销通过穿过连接器钻出的第一通道接合在连接器内并接触球形体导致球茎体向外膨胀，以及包括多个嵌入式插座并且直接连接到球根体的基座，其中底座接收连接器。

38. 发明申请

US20100309718A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100309718A1
公开(公告)日：2010-12-09
申请号：US12492434
申请日：2009-06-26
申请人： Young-Hoon Oh , Sung-Yeon Lee
发明人： Young-Hoon Oh , Sung-Yeon Lee
IPC分类号： G11C11/14 , G11C7/00 , G11C5/14 , G11C8/08
CPC分类号： G11C5/147 , G11C7/04 , G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/1697
摘要： A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation.
摘要翻译：半导体存储器件使用磁性隧道结器件（MTJ），并且包括连接在第一驱动线和第二驱动线之间的存储单元，并被配置为存储具有基于流过的电流的方向确定的数据状态的数据第一驱动线和第二驱动线，以及电流控制块，被配置为响应于写入操作中的温度信息来控制提供给第一和第二驱动线的电源电流。

39. 发明申请

US20100274094A1 Tissue Retraction Apparatus 审中-公开
标题翻译：组织收缩装置
公开(公告)号：US20100274094A1
公开(公告)日：2010-10-28
申请号：US12428641
申请日：2009-04-23
申请人： Mahmoud F. Abdelgany , Young Hoon Oh
发明人： Mahmoud F. Abdelgany , Young Hoon Oh
IPC分类号： A61B1/32
CPC分类号： A61B17/0293 , A61B17/0206
摘要： A tissue retraction apparatus comprising a first body including a first body lower surface with a plurality of tracks embedded therein; a second body coupled to the first body that allows rotational movement of the first body relative to the second body, the second body including a second body upper surface comprising a plurality of tracks embedded therein; and a plurality of dilation components axially spaced around a dynamic opening, each dilation component comprising an arm including a top and a bottom, where the arm is coupled to an arm track of the second body and allows translational movement of the arm along the arm track; a pin fixedly coupled to the top of the arm, wherein the pin is coupled to a track of the first body and allows translational movement of the pin along the track; and a leg fixedly coupled to the bottom of the arm.
摘要翻译：一种组织缩回装置，包括：第一主体，包括具有嵌入其中的多个轨道的第一主体下表面; 耦合到所述第一主体的第二主体，其允许所述第一主体相对于所述第二主体旋转运动，所述第二主体包括第二主体上表面，所述第二主体上表面包括嵌入其中的多个轨道; 以及围绕动态开口轴向间隔开的多个扩张部件，每个扩张部件包括一个包括顶部和底部的臂，其中所述臂连接到所述第二主体的臂轨道，并允许所述臂沿着所述臂轨迹的平移运动 ; 固定地联接到所述臂的顶部的销，其中所述销耦合到所述第一主体的轨道并且允许所述销沿着所述轨道的平移运动; 以及固定地联接到臂的底部的腿。

40. 发明申请

US20100195423A1 SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF 失效
公开(公告)号：US20100195423A1
公开(公告)日：2010-08-05
申请号：US12761734
申请日：2010-04-16
申请人： Young-Hoon OH
发明人： Young-Hoon OH
IPC分类号： G11C7/00 , H03L7/06 , G11C8/18
CPC分类号： H03L7/087 , H03L7/0812 , H03L7/093
摘要： A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.

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