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31. 发明授权

US07839672B1 Phase change memory array circuits and methods of manufacture 有权
标题翻译：相变存储器阵列电路和制造方法
公开(公告)号：US07839672B1
公开(公告)日：2010-11-23
申请号：US12002121
申请日：2007-12-14
申请人： Winston Lee , Peter Lee
发明人： Winston Lee , Peter Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0071
摘要： A memory array includes cells with switches and phase-change elements that are in communication with the switches. Bit lines are in communication with the cells. Word lines are in communication with the cells. Different voltage source terminals each receive a respective source voltage. The different voltage source terminals are coupled to and supply current to at least one of the cells.
摘要翻译：存储器阵列包括具有与开关通信的开关和相变元件的单元。位线与单元格通信。字线与单元格通信。不同的电压源端子各自接收相应的源极电压。不同的电压源端子耦合到电池并将电流提供给至少一个电池单元。

32. 发明授权

US07807539B1 Ion implantation and process sequence to form smaller base pick-up 有权
标题翻译：离子注入和工艺顺序形成较小的基座
公开(公告)号：US07807539B1
公开(公告)日：2010-10-05
申请号：US12056052
申请日：2008-03-26
申请人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L21/8222 , H01L21/331
CPC分类号： H01L29/0804 , H01L29/66272
摘要： Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first portion of the substrate, doping a second portion of the substrate with a second dopant to form at least one emitter region. A bipolar junction transistor device may include a floating collector, in which case the bipolar junction transistor device may be operated as a diode for improved emitter current.
摘要翻译：本文描述了用于形成双极结型晶体管器件的方法。用于形成双极结型晶体管器件的方法可以包括用第一掺杂剂掺杂衬底的第一部分以形成基极拾取区域，并且在掺杂衬底的第一部分之后，将衬底的第二部分用第二掺杂剂以形成至少一个发射极区域。双极结型晶体管器件可以包括浮动集电极，在这种情况下，双极结型晶体管器件可以作为二极管来工作，以改善发射极电流。

33. 发明授权

US07184290B1 Logic process DRAM 有权
标题翻译：逻辑处理DRAM
公开(公告)号：US07184290B1
公开(公告)日：2007-02-27
申请号：US11138681
申请日：2005-05-27
申请人： Winston Lee , Peter Lee , Sehat Sutardja
发明人： Winston Lee , Peter Lee , Sehat Sutardja
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/02 , G11C7/12 , G11C7/18 , G11C11/4094 , G11C11/4097 , H01L27/10885
摘要： A dynamic random access memory (DRAM) unit includes pluralities of bit line pairs and word lines. Each bit line pair includes first and second bit lines aligned with each other in an end-to-end arrangement. The first bit lines are arranged substantially parallel and consecutively adjacent to one another. The second bit lines are arranged substantially parallel and consecutively adjacent to one another. Each word line is associated with either the first bit lines or the second bit lines. A first array is formed by the first bit lines and the associated word lines. A second array is formed by the second bit lines and the associated word lines. Each of a plurality of memory cells is associated with every other bit line along each word line. Each of a plurality of multiplexers is in communication with two adjacent bits lines within one of the first and second arrays.
摘要翻译：动态随机存取存储器（DRAM）单元包括多个位线对和字线。每个位线对包括在端对端布置中彼此对准的第一和第二位线。第一位线基本上平行并且彼此相邻地布置。第二位线基本上平行并且彼此相邻地布置。每个字线与第一位线或第二位线相关联。第一阵列由第一位线和相关联的字线形成。第二阵列由第二位线和相关联的字线形成。多个存储器单元中的每一个与沿着每个字线的每隔一个位线相关联。多个复用器中的每一个与第一和第二阵列之一内的两个相邻位线连通。

34. 发明授权

US06570781B1 Logic process DRAM 有权
标题翻译：逻辑处理DRAM
公开(公告)号：US06570781B1
公开(公告)日：2003-05-27
申请号：US09881474
申请日：2001-06-14
申请人： Winston Lee , Peter Lee , Sehat Sutardja
发明人： Winston Lee , Peter Lee , Sehat Sutardja
IPC分类号： G11C700
CPC分类号： H01L27/10885 , G11C11/4097 , H01L23/5225 , H01L27/0207 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.
摘要翻译：提供了包括具有提高的信噪比，降低的位线电容和减小的面积的动态随机存取存储器（DRAM）单元的半导体集成电路器件。 DRAM单元包括多个位线对，每个位线对包括第一金属导体和第二金属导体。每个位线对包括参考位线和感测位线。每个位线对可以被配置为使得参考位线和感测位线相对于彼此纵向定向。或者，每个位线对被配置为使得第一金属导体和第二金属导体在至少一个位置上彼此对称地扭曲。单元板和晶体管栅极之间的横向间隔最小化，导致总面积减小。

35. 发明授权

US5163021A Multi-state EEprom read and write circuits and techniques 失效
标题翻译：多状态EEprom读写电路和技术
公开(公告)号：US5163021A
公开(公告)日：1992-11-10
申请号：US734221
申请日：1991-07-22
申请人： Sanjay Mehrotra , Eliyahou Harari , Winston Lee
发明人： Sanjay Mehrotra , Eliyahou Harari , Winston Lee
IPC分类号： G11C11/56 , G11C16/10 , G11C16/16 , G11C16/34
CPC分类号： G11C7/04 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5631 , G11C2211/5634 , G11C2211/5645
摘要： Improvements in the circuits and techniques for read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.
摘要翻译：用于读，写和擦除EEprom存储器的电路和技术的改进使非易失性多状态存储器能够在更长的时间内以更高的性能运行。在用于正常读取和用于读取或擦除之间的读取和读取的改进电路进行验证之前，相对于由对应的一组参考单元提供的一组阈值电平进行读取，所述一组参考单元紧密地跟踪和调整由存储器呈现的变化细胞。在一个实施例中，存储器单元的每个闪存扇区具有其自己的用于读取扇区中的单元的参考单元，并且对于用作主参考的整个存储器芯片也存在一组参考单元。在另一个实施例中，通过一对多电流镜像电路同时进行相对于一组阈值电平的读取。在改进的写入或擦除电路中，写入或擦除的数据的验证一次在一组存储器单元上并行完成，并且电路选择性地禁止对已经被正确验证的那些单元进一步写入或擦除。其他改进包括对擦除后的基准状态进行编程，独立和可变的电源为EEprom存储器单元的控制栅极。

36. 发明授权

US08472277B2 System and method for memory array decoding 有权
标题翻译：用于存储器阵列解码的系统和方法
公开(公告)号：US08472277B2
公开(公告)日：2013-06-25
申请号：US13527119
申请日：2012-06-19
申请人： Pantas Sutardja , Winston Lee
发明人： Pantas Sutardja , Winston Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/10 , G11C7/00 , G11C7/1006 , G11C7/18 , G11C8/12 , G11C8/14 , G11C2207/2209
摘要： A memory system includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells, and a read/write module. The bit lines include a first bit line and a second bit line. The word lines include a first word line and a second word line. Each memory cell is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory cells include a first memory cell and a second memory cell. The first memory cell is located at the intersection of the first bit line and the first word line. The second memory cell is located at the intersection of the second bit line and the second word line. The read/write module is configured to concurrently activate the first memory cell and the second memory cell for (i) a read operation or (ii) a write operation.
摘要翻译：存储器系统包括多个位线，多个字线，多个存储器单元和读/写模块。位线包括第一位线和第二位线。字线包括第一字线和第二字线。每个存储器单元位于相应的一个位线和相应的字线之间的交叉点处。存储单元包括第一存储单元和第二存储单元。第一存储单元位于第一位线和第一字线的交点处。第二存储单元位于第二位线和第二字线的交点处。读/写模块被配置为同时激活第一存储器单元和第二存储器单元，用于（i）读取操作或（ii）写入操作。

37. 发明申请

US20120068754A1 METHOD AND APPARATUS FOR TIMING CLOSURE 失效
标题翻译：用于定时关闭的方法和装置
公开(公告)号：US20120068754A1
公开(公告)日：2012-03-22
申请号：US13235908
申请日：2011-09-19
申请人： Jason T. SU , Winston Lee
发明人： Jason T. SU , Winston Lee
IPC分类号： H03H11/26
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84 , H03K5/159 , H03K2005/00013
摘要： Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.
摘要翻译：本公开的方面提供了诸如集成电路的电路。电路包括第一电路和第二电路。第二电路包括延迟电路，其被配置为响应于制造，环境和操作参数（例如过程变化，温度变化和电源电压）的至少一个参数变化，使得第二电路具有基本匹配的第一电路的延迟特性变异。

38. 发明授权

US07939445B1 High density via and metal interconnect structures, and methods of forming the same 有权
标题翻译：高密度通孔和金属互连结构及其形成方法
公开(公告)号：US07939445B1
公开(公告)日：2011-05-10
申请号：US12049229
申请日：2008-03-14
申请人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838
摘要： Methods and structures for interconnects in semiconductor devices are described. A method of forming a mask pattern for a metal layer in an interconnect can include searching a layout for a metal feature with a predetermined size and an interconnect layer aligned thereto, removing the metal feature from the layout to form a modified layout, and reforming the mask pattern using the modified layout. The metal interconnect may include a first pattern of metal lines, each having a minimum feature size in a layout view in no more than one dimension; a dielectric layer on or over the first pattern of metal lines, having a substantially planar horizontal upper surface; and vias or contacts in the dielectric layer, the vias or contacts contacting a top surface of the first pattern of metal lines and a top surface of silicon structures, vias, or contacts below the first pattern of metal lines.
摘要翻译：描述了半导体器件中互连的方法和结构。在互连中形成用于金属层的掩模图案的方法可以包括搜索具有预定尺寸的金属特征的布局和与其对准的互连层，从布局去除金属特征以形成修改的布局，并且重新形成掩模图案使用修改的布局。金属互连可以包括金属线的第一图案，每个金属线在布局视图中具有不超过一个维度的最小特征尺寸; 金属线的第一图案上或之上的介电层，具有基本上平面的水平上表面; 以及电介质层中的通孔或触点，接触金属线的第一图案的顶表面的通孔或触点以及金属线的第一图案之下的硅结构，通孔或触点的顶表面。

39. 发明授权

US07734966B1 Method and system for memory testing and test data reporting during memory testing 有权
标题翻译：内存测试中的内存测试和测试数据报告的方法和系统
公开(公告)号：US07734966B1
公开(公告)日：2010-06-08
申请号：US11679133
申请日：2007-02-26
申请人： Winston Lee , Albert Wu , Chorng-Lii Liou
发明人： Winston Lee , Albert Wu , Chorng-Lii Liou
IPC分类号： G11C29/00
CPC分类号： G06F11/2094 , G11C29/00 , G11C29/12 , G11C29/12015 , G11C29/14 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/48 , G11C29/56 , G11C29/72 , G11C2029/1208 , G11C2029/5602
摘要： The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources. The present invention further provides a redundant resource allocation system, which uses a bad location list and an associated bad location list to classify failed memory locations according to a predetermined priority sequence, and allocates redundant resources to repair the failed memory locations according to the priority sequence.
摘要翻译：本发明提供了一种用于提高存储器测试效率，提高存储器测试速度，检测在存储器工作频率下发生的存储器故障以及减少冗余修复分析报告的数据的方法和系统。存储器测试系统包括第一存储器测试器，以较高的存储器工作频率从存储器提取故障存储器位置信息，外部存储器测试器以较低的存储器测试器频率接收失败的存储器位置信息，以及第一存储器测试器与外部存储器测试仪。存储器测试方法使用存储器测试器频率处的数据选通来计时在较高存储器工作频率处获得的故障存储器位置信息。此外，本发明的方法仅向外部存储器测试器报告足够的信息，以确定可用冗余资源可修复的行，列和单位故障。本发明还提供了一种冗余资源分配系统，其使用不良位置列表和相关联的不良位置列表来根据预定的优先顺序对失败的存储器位置进行分类，并且根据优先顺序分配冗余资源来修复失效的存储器位置。

40. 发明授权

US07596011B1 Logic process DRAM 失效
标题翻译：逻辑处理DRAM
公开(公告)号：US07596011B1
公开(公告)日：2009-09-29
申请号：US11710818
申请日：2007-02-26
申请人： Winston Lee , Peter Lee , Sehat Sutardja
发明人： Winston Lee , Peter Lee , Sehat Sutardja
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/02 , G11C7/12 , G11C7/18 , G11C11/4094 , G11C11/4097 , H01L27/10885
摘要： An integrated circuit device comprises a plurality of bit line pairs. First and second bit lines are aligned with each other in an end-to-end arrangement. The first and second bit lines are arranged consecutively adjacent to one another, respectively. A plurality of word lines is associated with the first bit lines and the second bit lines. A first array includes the first bit lines and first associated ones of the plurality of word lines, and wherein a second array includes the second bit lines and second ones of the plurality of associated word lines. A first plurality of multiplexers communicates with two adjacent bits lines within one of the first and second arrays. The first array operates as a sense array and the second array operates as a reference array when at least one of the plurality of word lines is active in the first array.
摘要翻译：集成电路装置包括多个位线对。第一和第二位线在端对端布置中彼此对准。第一和第二位线分别彼此相邻布置。多个字线与第一位线和第二位线相关联。第一阵列包括第一位线和多个字线中的第一相关联的线，并且其中第二阵列包括第二位线和多个关联字线中的第二位线。第一多个复用器与第一和第二阵列之一内的两个相邻位线通信。当第一阵列中的至少一个字线处于活动状态时，第一阵列作为感测阵列工作，而第二阵列作为参考阵列工作。

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