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    • 34. 发明授权
    • Programmable buffer
    • 可编程缓冲器
    • US08324934B1
    • 2012-12-04
    • US13007688
    • 2011-01-17
    • Keith TruongJohn SchadtRavi LallWilliam Andrews
    • Keith TruongJohn SchadtRavi LallWilliam Andrews
    • H03K19/094
    • H03K19/0941H03K3/0377
    • In one embodiment of the invention, a programmable device, such as an FPGA, has a programmable input buffer with a VCCIO-powered buffer stage for high-voltage signaling and a VCC-powered buffer stage for low-voltage signaling. In addition to a main driver section, the VCCIO-powered buffer stage has a mixed-mode section for handling multiple different over-drive and multiple different under-drive conditions, a hysteresis section for providing multiple different trip-point hysteresis modes of operation, and a level-shifting section with look-ahead circuitry that enables the main driver section to be implemented with low-power, high-threshold devices, while still enabling the VCCIO-powered buffer stage to operate with low skew and high speed.
    • 在本发明的一个实施例中,诸如FPGA的可编程器件具有可编程输入缓冲器,其具有用于高电压信号的VCCIO供电缓冲级和用于低电压信号的VCC供电缓冲级。 除主驱动器部分外,VCCIO供电的缓冲级具有混合模式部分,用于处理多个不同的过驱动和多个不同的驱动下条件,滞后部分用于提供多种不同的跳变点滞后操作模式, 以及具有先行电路的电平转换部分,其使得主驱动器部分能够用低功率,高阈值器件实现,同时仍然使得VCCIO供电的缓冲器级以低歪斜和高速度运行。
    • 39. 发明申请
    • Temperature-independent, linear on-chip termination resistance
    • 温度独立,线性片上终端电阻
    • US20070164844A1
    • 2007-07-19
    • US11300886
    • 2005-12-15
    • Mou LinWilliam AndrewsJohn Schadt
    • Mou LinWilliam AndrewsJohn Schadt
    • H01C7/00
    • H04L25/0298H01L28/20
    • In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.
    • 在本发明的一个实施例中,诸如FPGA的集成电路具有一个或多个可编程端接方案,每个可编程端接方案具有并联连接的多个电阻端接支路,以及被设计成控制每个端接方案用于处理电压的校准电路 ,和温度(PVT)变化。 校准电路中的感测元件和每个端接方案中的每个电阻支路具有与非硅化聚(NSP)电阻器串联连接的基于晶体管的传输栅极。 每个NSP电阻器的负温度系数抵消相应传输门的电阻率的正温度系数,以提供与温度无关的感测元件和温度独立的端接脚。 感测元件和终端支路的温度独立性和恒定IV特性使得单个校准电路能够同时控制在不同终端电压电平下工作的多个终端方案。