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31. 发明授权

US08004066B2 Crack stop and moisture barrier 有权
标题翻译：破裂停止和防潮
公开(公告)号：US08004066B2
公开(公告)日：2011-08-23
申请号：US12766709
申请日：2010-04-23
申请人： Sun-Oo Kim , O Seo Park
发明人： Sun-Oo Kim , O Seo Park
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L23/562 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line. The discrete conductive features may comprise a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a combination of both.
摘要翻译：用于半导体器件的裂纹阻挡和湿气屏障的设计包括形成在靠近划线的集成电路的边缘处的多个离散的导电特征。离散的导电特征可以包括多个交错线，多个马蹄形线，或两者的组合。

32. 发明授权

US07960811B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07960811B2
公开(公告)日：2011-06-14
申请号：US12059457
申请日：2008-03-31
申请人： Sun-Oo Kim
发明人： Sun-Oo Kim
IPC分类号： H01L29/72
CPC分类号： H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Capacitor plates, capacitors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes at least one via and at least one conductive member coupled to the at least one via. The at least one conductive member comprises an enlarged region proximate the at least one via.
摘要翻译：公开了电容器板，电容器，半导体器件及其制造方法。在一个实施例中，电容器板包括耦合到至少一个通孔的至少一个通孔和至少一个导电构件。所述至少一个导电构件包括靠近所述至少一个通孔的放大区域。

33. 发明授权

US07939942B2 Semiconductor devices and methods of manufacturing thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07939942B2
公开(公告)日：2011-05-10
申请号：US11960195
申请日：2007-12-19
申请人： O Seo Park , Sun-Oo Kim , Klaus Herold
发明人： O Seo Park , Sun-Oo Kim , Klaus Herold
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/5226 , G03F1/00 , G03F1/36 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.
摘要翻译：公开了半导体器件，其制造方法，光刻掩模和设计光刻掩模的方法。在一个实施例中，半导体器件包括设置在第一材料层中的多个第一特征。至少一个第二特征被布置在第二材料层中，所述至少一个第二特征被布置在多个第一特征上并耦合到多个第一特征。至少一个第二特征包括设置在多个第一特征中的至少两个之间的至少一个空隙。

34. 发明授权

US07795615B2 Capacitor integrated in a structure surrounding a die 有权
标题翻译：电容器集成在一个模具周围的结构中
公开(公告)号：US07795615B2
公开(公告)日：2010-09-14
申请号：US11268854
申请日：2005-11-08
申请人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
发明人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
IPC分类号： H01L23/58
CPC分类号： H01L23/5223 , H01L23/585 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprises a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip. The integrated circuitry is disposed within the circuit area. No active circuit is disposed within the peripheral area. A barrier is disposed within the peripheral area and surrounds the circuit area. The barrier includes a capacitor structure integrated therein.
摘要翻译：集成电路包括芯片，该芯片包括由周边区域包围的电路区域，该周边区域延伸到芯片的边缘。集成电路设置在电路区域内。外围区域内没有设置有源电路。屏障设置在外围区域内并且围绕电路区域。屏障包括集成在其中的电容器结构。

35. 发明申请

US20100022085A1 Method of Forming Support Structures for Semiconductor Devices 有权
标题翻译：形成半导体器件支撑结构的方法
公开(公告)号：US20100022085A1
公开(公告)日：2010-01-28
申请号：US12572905
申请日：2009-10-02
申请人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
发明人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
IPC分类号： H01L21/768 , G06F17/50
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/20754 , H01L2924/30105 , H01L2924/00 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20755 , H01L2224/05599
摘要： Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.
摘要翻译：公开了半导体器件的支撑结构及其制造方法。在一些实施例中，支撑结构包括在线接合区域下方形成为大致环形的多个支撑构件。多个支撑构件的大致环形形状内的中心区域可以用于路由功能导电线，用于与半导体器件的有源区电接触。可选地，在功能导电线之间形成虚拟支撑结构。支撑结构可以形成在半导体器件的一个或多个导电层和半导体材料层中。在其它实施例中，支撑构件不形成为环形，并且形成为不包括低介电常数（k）材料的绝缘层。

36. 发明申请

US20090160062A1 Semiconductor Devices and Methods of Manufacturing Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090160062A1
公开(公告)日：2009-06-25
申请号：US11960195
申请日：2007-12-19
申请人： O. Seo Park , Sun-Oo Kim , Klaus Herold
发明人： O. Seo Park , Sun-Oo Kim , Klaus Herold
IPC分类号： H01L23/52 , H01L21/4763 , G03F1/00
CPC分类号： H01L23/5226 , G03F1/00 , G03F1/36 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.
摘要翻译：公开了半导体器件，其制造方法，光刻掩模和设计光刻掩模的方法。在一个实施例中，半导体器件包括设置在第一材料层中的多个第一特征。至少一个第二特征被布置在第二材料层中，所述至少一个第二特征被布置在多个第一特征上并耦合到多个第一特征。至少一个第二特征包括设置在多个第一特征中的至少两个之间的至少一个空隙。

37. 发明申请

US20070102787A1 Capacitor integrated in a structure surrounding a die 有权
标题翻译：电容器集成在一个模具周围的结构中
公开(公告)号：US20070102787A1
公开(公告)日：2007-05-10
申请号：US11268854
申请日：2005-11-08
申请人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
发明人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/585 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprises a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip. The integrated circuitry is disposed within the circuit area. No active circuit is disposed within the peripheral area. A barrier is disposed within the peripheral area and surrounds the circuit area. The barrier includes a capacitor structure integrated therein.
摘要翻译：集成电路包括芯片，该芯片包括由周边区域包围的电路区域，该周边区域延伸到芯片的边缘。集成电路设置在电路区域内。外围区域内没有设置有源电路。屏障设置在外围区域内并且围绕电路区域。屏障包括集成在其中的电容器结构。

38. 发明申请

US20070080464A1 Support structures for semiconductor devices 有权
标题翻译：半导体器件的支撑结构
公开(公告)号：US20070080464A1
公开(公告)日：2007-04-12
申请号：US11248554
申请日：2005-10-12
申请人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
发明人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/20754 , H01L2924/30105 , H01L2924/00 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20755 , H01L2224/05599
摘要： Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.
摘要翻译：公开了半导体器件的支撑结构及其制造方法。在一些实施例中，支撑结构包括在线接合区域下方形成为大致环形的多个支撑构件。多个支撑构件的大致环形形状内的中心区域可以用于路由功能导电线，用于与半导体器件的有源区电接触。可选地，在功能导电线之间形成虚拟支撑结构。支撑结构可以形成在半导体器件的一个或多个导电层和半导体材料层中。在其它实施例中，支撑构件不形成为环形，并且形成为不包括低介电常数（k）材料的绝缘层。

39. 发明授权

US07112507B2 MIM capacitor structure and method of fabrication 有权
标题翻译： MIM电容器结构及其制造方法
公开(公告)号：US07112507B2
公开(公告)日：2006-09-26
申请号：US10720450
申请日：2003-11-24
申请人： Sun-Oo Kim , Ernst Demm
发明人： Sun-Oo Kim , Ernst Demm
IPC分类号： H01L21/20
CPC分类号： H01L28/60 , H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness of the metallization layer, thus improving the reliability of the MIM capacitor. The thin conductive material layer may comprise TiN, TaN, or WN and may alternatively comprise a barrier layer disposed over or under the TiN, TaN, or WN. One plate of the MIM capacitor is patterned using the same mask that is used to pattern conductive lines in a metallization layer, thus reducing the number of masks that are required to manufacture the MIM capacitor.
摘要翻译：一种形成金属绝缘体金属（MIM）电容器的方法，其中在半导体器件的金属化层的整个厚度上形成MIM电容器的板。至少一个薄导电材料层设置在金属化层的材料内，以减小金属化层的表面粗糙度，从而提高MIM电容器的可靠性。薄导电材料层可以包括TiN，TaN或WN，并且还可以包括设置在TiN，TaN或WN之上或之下的阻挡层。使用与用于在金属化层中形成导线的掩模相同的掩模对MIM电容器的一个板进行构图，从而减少制造MIM电容器所需的掩模的数量。

40. 发明授权

US07052990B2 Sealed pores in low-k material damascene conductive structures 有权
标题翻译：低k材料镶嵌导电结构中的密封孔
公开(公告)号：US07052990B2
公开(公告)日：2006-05-30
申请号：US10654143
申请日：2003-09-03
申请人： Sun-Oo Kim
发明人： Sun-Oo Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807
摘要： An oxide layer is used to seal pores in porous low-dielectric constant materials, thus preventing the migration of subsequently deposited copper materials into the porous low-dielectric constant materials in damascene processes. The oxide layer is deposited over the inner surface of at least one pore along a sidewall of the patterned low-dielectric constant material. In one embodiment, the oxide layer is deposited using atomic layer deposition (ALD), and the oxide layer comprises SiO2.
摘要翻译：使用氧化物层来密封多孔低介电常数材料中的孔，从而防止随后沉积的铜材料在镶嵌工艺中迁移到多孔低介电常数材料中。氧化物层沿图案化的低介电常数材料的侧壁沉积在至少一个孔的内表面上。在一个实施例中，使用原子层沉积（ALD）沉积氧化物层，并且氧化物层包含SiO 2。

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