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31. 发明授权

US07631207B1 Reducing power consumption for processing of common values in microprocessor registers and execution units 有权
标题翻译：降低处理微处理器寄存器和执行单元中常用值的功耗
公开(公告)号：US07631207B1
公开(公告)日：2009-12-08
申请号：US11408784
申请日：2006-04-21
申请人： Seungyoon Peter Song , Jorel Hartman
发明人： Seungyoon Peter Song , Jorel Hartman
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F9/30141 , G06F9/30156 , G06F9/3016 , G06F9/3017 , G06F9/383
摘要： Reducing power consumption in microprocessors for the processing of common values. Common values provided in at least one received operation are encoded into encoded common values having a lower number of bits than the common values prior to encoding. In one aspect, a separate encoding bus is used to provide the encoded common values in various processing of additional received operations in the microprocessor instead of a full-bit bus of the microprocessor, the encoding bus having less bits than the full-bit bus. In another aspect, a result of the operation is predicted based on at least one encoded common value and execution of the operation is bypassed.
摘要翻译：微处理器的功耗降低，用于处理普通值。在至少一个接收到的操作中提供的公共值被编码成具有比编码之前的公共值低的位数的编码公共值。在一个方面，单独的编码总线用于在微处理器中的附加接收操作的各种处理中提供编码的公共值，而不是微处理器的全位总线，编码总线具有比全位总线更少的位。在另一方面，基于至少一个编码的公共值来预测操作的结果，并且绕过该操作的执行。

32. 发明授权

US07568088B1 Flag management in processors enabled for speculative execution of micro-operation traces 有权
标题翻译：处理器中的标志管理能够推测微操作轨迹的执行
公开(公告)号：US07568088B1
公开(公告)日：2009-07-28
申请号：US11553455
申请日：2006-10-26
申请人： John Gregory Favor , Seungyoon Peter Song , Christopher P. Nelson
发明人： John Gregory Favor , Seungyoon Peter Song , Christopher P. Nelson
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30094 , G06F9/3808 , G06F9/3863
摘要： Managing speculative execution via groups of one or more actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flag values at atomic trace boundaries. Checkpointing flags on-demand for atomic traces in a processor system uses a flag checkpoint table to store a plurality of flag checkpoints, each corresponding to an atomic trace. The table is selectively accessed to provide flag information to restore speculative flags when an atomic trace is aborted. A corresponding flag checkpoint is allocated to an invalid state when an atomic trace is renamed. An action that updates flags initializes the corresponding flag checkpoint (if invalid). If the atomic trace is aborted, then the table is searched according to program order starting with the entry corresponding to the aborted atomic trace. The first (if any) valid checkpoint found is used for flag restoration.
摘要翻译：通过与原子轨迹对应的一个或多个动作的组来管理推测性执行，可以有效地处理与标志相关的动作，因为原子轨迹有利地使原子轨迹边界上的标志值的检查点成为可能。处理器系统中原子轨迹的点对点标志使用标志检查点表来存储多个对应于原子轨迹的标志检查点。当原子轨迹中止时，有选择地访问该表以提供标志信息来恢复推测标志。当重命名原子轨迹时，相应的标志检查点被分配到无效状态。更新标志的动作初始化相应的标志检查点（如果无效）。如果原子轨迹被中止，那么根据程序顺序搜索表格，从与中止的原子轨迹对应的条目开始。找到的第一个（如果有的话）有效检查点用于标志恢复。

33. 发明申请

US20090132764A1 POWER CONSERVATION VIA DRAM ACCESS 有权
标题翻译：通过DRAM访问进行功率保存
公开(公告)号：US20090132764A1
公开(公告)日：2009-05-21
申请号：US11559192
申请日：2006-11-13
申请人： Laurent R. MOLL , Seungyoon Peter SONG , Peter N. GLASKOWSKY , Yu Qing CHENG
发明人： Laurent R. MOLL , Seungyoon Peter SONG , Peter N. GLASKOWSKY , Yu Qing CHENG
IPC分类号： G06F12/08
CPC分类号： G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F12/0802 , G06F12/0888 , G06F2212/2515 , Y02D10/13 , Y02D10/14
摘要： Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.
摘要翻译：通过DRAM访问减少的功率节省由在正常模式和缓冲模式下选择性地操作的缓冲器/微型缓存器提供。在缓冲模式下，当CPU开始在低功率状态下运行时，与缓存/存储器相关的特定物理地址范围匹配或具有访问本身的特定特性的非可缓存访问（例如DMA设备生成）微型缓存，而不是由存储器控制器和DRAM。缓冲/微型缓存处理包括在引用未命中时分配线路，以及当引用命中时从缓冲器/微型缓存器返回缓存数据。根据多个替换策略中的一个替换策略，在缓冲器/微型缓存中替换行，包括当没有可用的空行时停止替换。在正常模式下，当CPU开始在高功率状态下运行时，缓冲器/微型缓存类似于常规高速缓存，并且不能处理非缓存访问。

34. 发明授权

US07412570B2 Small and power-efficient cache that can provide data for background DNA devices while the processor is in a low-power state 有权
标题翻译：小而高功率的缓存，可在处理器处于低功耗状态时为背景DNA设备提供数据
公开(公告)号：US07412570B2
公开(公告)日：2008-08-12
申请号：US11351058
申请日：2006-02-09
申请人： Laurent R. Moll , Yu Qing Cheng , Peter N. Glaskowsky , Seungyoon Peter Song
发明人： Laurent R. Moll , Yu Qing Cheng , Peter N. Glaskowsky , Seungyoon Peter Song
IPC分类号： G06F13/14
CPC分类号： G06F12/0835 , G06F12/0875 , G06F13/28 , G06F2212/1028 , Y02D10/13
摘要： A small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).
摘要翻译：当微处理器中的高速缓存数据由于微处理器中的任何一个或全部处于低电平状态而无法访问时，小型和功率高效的缓冲器/微型缓存器将选择的DMA访问定向到微处理器的相干域中的存储器空间电源状态不支持窥探。通过缓冲器/微型缓存来满足所选择的DMA访问通过允许微处理器（或其一部分）保持在低功率状态来降低功耗。缓冲器/微型高速缓存可以相对于微处理器中的高速缓存数据非相干地操作（暂时地），并且在微处理器（或其部分）转换到启用窥探的高功率状态之前，在去激活之前刷新以与缓存数据同步。或者，缓冲器/微型缓存可以以与缓存的数据相一致的方式（递增地）操作。微处理器实现具有相关联的高速缓存系统（例如第一，第二和更高级别高速缓存的各种布置）的一个或多个处理器。

35. 发明授权

US07389403B1 Adaptive computing ensemble microprocessor architecture 有权
标题翻译：自适应计算集成微处理器架构
公开(公告)号：US07389403B1
公开(公告)日：2008-06-17
申请号：US11277761
申请日：2006-03-29
申请人： Donald B. Alpert , John Gregory Favor , Peter N. Glaskowsky , Seungyoon Peter Song
发明人： Donald B. Alpert , John Gregory Favor , Peter N. Glaskowsky , Seungyoon Peter Song
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/30181 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： An Adaptive Computing Ensemble (ACE) includes a plurality of flexible computation units as well as an execution controller to allocate the units to Computing Ensembles (CEs) and to assign threads to the CEs. The units may be any combination of ACE-enabled units, including instruction fetch and decode units, integer execution and pipeline control units, floating-point execution units, segmentation units, special-purpose units, reconfigurable units, and memory units. Some of the units may be replicated, e.g. there may be a plurality of integer execution and pipeline control units. Some of the units may be present in a plurality of implementations, varying by performance, power usage, or both. The execution controller dynamically alters the allocation of units to threads in response to changing performance and power consumption observed behaviors and requirements. The execution controller also dynamically alters performance and power characteristics of the ACE-enabled units, according to the observed behaviors and requirements.
摘要翻译：自适应计算集合（ACE）包括多个灵活的计算单元以及将单元分配给计算集合（CE）并将线程分配给CE的执行控制器。单元可以是启用ACE的单元的任何组合，包括指令提取和解码单元，整数执行和流水线控制单元，浮点执行单元，分段单元，专用单元，可重配置单元和存储单元。一些单位可能被复制，例如可以存在多个整数执行和流水线控制单元。一些单元可以存在于由性能，功率使用或两者变化的多个实现中。响应于观察到的行为和要求的性能和功耗的变化，执行控制器动态地改变单元对线程的分配。执行控制器还根据观察到的行为和要求动态地改变启用ACE的单元的性能和功率特性。

36. 发明授权

US5761723A Data processor with branch prediction and method of operation 失效
标题翻译：具有分支预测和操作方法的数据处理器
公开(公告)号：US5761723A
公开(公告)日：1998-06-02
申请号：US637189
申请日：1996-04-08
申请人： Bryan P. Black , Marvin Denman , Mark A. Kearney , Seungyoon Peter Song
发明人： Bryan P. Black , Marvin Denman , Mark A. Kearney , Seungyoon Peter Song
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3861
摘要： A data processor (10) has a branch target address cache (48) for storing the target addresses of a number of recently taken branch instructions. Normally, each fetch address is compared to the contents of the branch target address cache. If a hit occurs, then the data processor branches to the cached target address. The data processor also has a dispatch unit (60) that invalidates the data stored in the branch target address cache if and when it determines that the branch target address cache "hit" on an instruction that was not a branch instruction at all, a "phantom branch." The data processor thereby automatically invalidates its branch target address cache data after a context switch.
摘要翻译：数据处理器（10）具有分支目标地址高速缓冲存储器（48），用于存储多个最近采取的分支指令的目标地址。通常，将每个获取地址与分支目标地址高速缓存的内容进行比较。如果发生命中，则数据处理器分支到缓存的目标地址。数据处理器还具有一个调度单元（60），当分支目标地址缓存器确定分支目标地址高速缓冲存储器“完全不是分支指令”的指令时，使分配目标地址缓存中存储的数据无效，幻影分支“。因此，数据处理器在上下文切换之后自动使其分支目标地址高速缓存数据失效。

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