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    • 31. 发明授权
    • Bus data transmission apparatus, method for transmitting bus data and bus data communication apparatus
    • 总线数据传输装置,总线数据传输方法和总线数据通信装置
    • US08055823B2
    • 2011-11-08
    • US12541846
    • 2009-08-14
    • Jae Sung LeeSeong Woon Kim
    • Jae Sung LeeSeong Woon Kim
    • G06F13/38
    • G06F13/4217Y02D10/14Y02D10/151
    • Provided are a method and an apparatus for compression transmission of bus data including a plurality of bytes including upper bits and lower bits. The apparatus includes a comparator and an aligner. The comparator compares upper bits of a previous byte with upper bits of a current byte among the plurality of bytes. If the upper bits of the previous byte are identical to the upper bits of the current byte, the aligner compresses the bus data in a combination of a full-byte and a half-byte, by allowing the previous byte to be constituted with the full-byte having bits corresponding to the number of bits of the previous byte and allowing the current byte to be constituted with the half-byte excluding the upper bits of the current byte. Then, the aligner arrays the compressed bus data in a preset bus bandwidth to transmit to a slave device.
    • 提供了一种用于压缩传输包括高位和低位的多个字节的总线数据的方法和装置。 该装置包括比较器和对准器。 比较器将先前字节的高位与多个字节中的当前字节的高位进行比较。 如果前一个字节的高位与当前字节的高位相同,则对齐器以全字节和半字节的组合来压缩总线数据,通过允许前一个字节由完整字节组成 字节具有与先前字节的比特数相对应的比特,并允许当前字节由不包括当前字节的高位的半字节构成。 然后,对准器将预设总线带宽中的压缩总线数据排列成从属设备。
    • 34. 发明授权
    • Delay insensitive data transfer apparatus with low power consumption
    • 延迟不敏感的数据传输设备,功耗低
    • US07885254B2
    • 2011-02-08
    • US11927972
    • 2007-10-30
    • Myeong-Hoon OhSeong-Woon KimMyung-Joon Kim
    • Myeong-Hoon OhSeong-Woon KimMyung-Joon Kim
    • H04L12/50H04L12/28
    • H04L25/49H04L25/0264H04L25/4906
    • Provided is a delay insensitive (DI) data transfer apparatus with low power consumption. The apparatus, includes: N number of encoders configured to receive and encode input request and data signals, where each of the N number of encoders includes: a reference current source circuit configured to generate a current; and a voltage-to-current converter circuit configured to output a current having a level of 0, output the current having the level of I, and output the current having the level of 2I; and N number of decoders configured to recover the current-level signals, where each of the decoders includes: a threshold current source circuit configured to generate first and second threshold currents; an input current mirror circuit configured to differentiate the first and second threshold currents; and a current-to-voltage converter circuit configured to detect the threshold current, recover a voltage input value, and extract data and request signals.
    • 提供具有低功耗的延迟不敏感(DI)数据传送装置。 该装置包括:N个编码器,被配置为接收和编码输入请求和数据信号,其中N个编码器中的每一个包括:参考电流源电路,被配置为产生电流; 以及电压 - 电流转换器电路,被配置为输出电平为0的电流,输出具有电平I的电流,并输出电平为2I的电流; N个解码器被配置为恢复当前电平信号,其中每个解码器包括:阈值电流源电路,被配置为产生第一和第二阈值电流; 配置成区分第一和第二阈值电流的输入电流镜电路; 以及电流 - 电压转换器电路,被配置为检测阈值电流,恢复电压输入值,并提取数据和请求信号。
    • 36. 发明授权
    • Hardware device and method for transmitting network protocol packet
    • 用于传输网络协议包的硬件设备和方法
    • US07818460B2
    • 2010-10-19
    • US11949127
    • 2007-12-03
    • Sun-Wook KimDae-Won KimYoungwoo KimKyoung ParkSeong-Woon Kim
    • Sun-Wook KimDae-Won KimYoungwoo KimKyoung ParkSeong-Woon Kim
    • G06F15/16G06F15/173
    • H04L69/16H04L47/15H04L47/70H04L47/829H04L69/161H04L69/162
    • Provided are a hardware device and method for transmitting a network protocol packet in a TOE for network protocol acceleration. The hardware device includes: a socket resource control and TCP connection/release command unit for storing socket resource control commands, and TCP connection/release commands from a host processor; a message transmission command storing unit for storing message transmission commands based on network protocol corresponding to each socket; a socket information and packet transmission information storing unit for storing socket information and packet transmission information; and a transmission-only processor for checking necessary transmission resources by interpreting message transmission commands stored in the message transmission command storing unit, processing a message to be transmitted in a form of a network packet, reading data to be transmitted, creating a header, and storing socket information and packet transmission information in the socket information and packet transmission information storing unit.
    • 提供了一种用于在TOE中发送网络协议分组以进行网络协议加速的硬件设备和方法。 硬件设备包括:用于存储套接字资源控制命令的套接字资源控制和TCP连接/释放命令单元,以及来自主机处理器的TCP连接/释放命令; 消息发送命令存储单元,用于基于与每个插座相对应的网络协议来存储消息传输命令; 套接字信息和分组传输信息存储单元,用于存储套接字信息和分组传输信息; 以及仅传输处理器,用于通过解释存储在消息传输命令存储单元中的消息传输命令来检查必要的传输资源,处理以网络分组的形式发送的消息,读取要发送的数据,创建报头,以及 在套接字信息和分组发送信息存储单元中存储套接字信息和分组传输信息。
    • 39. 发明授权
    • Multi-processor system and method for controlling reset and processor ID thereof
    • 多处理器系统及其控制方法及其处理器ID
    • US07734903B2
    • 2010-06-08
    • US11633811
    • 2006-12-05
    • Young Woo KimSung Nam KimKyoung ParkSeong Woon KimMyung Joon Kim
    • Young Woo KimSung Nam KimKyoung ParkSeong Woon KimMyung Joon Kim
    • G06F9/00
    • G06F15/02G06F15/16
    • Provided are a microprocessor suitable for constructing a multi-processor system and a method for controlling the reset and processor ID of the microprocessor. The microprocessor includes decoder receiving a reset ID having a predetermined binary value and a reset signal and decoding the reset ID, an ID generator receiving the decoding result of the decoder and generating at least one microprocessor ID and a reset ID of a microprocessor serially connected to the microprocessor, and a reset vector unit selecting a reset vector according to the decoding result of the decoder. The multi-processor system is constructed such that independent microprocessors of the system respectively generate their own reset vectors and processor IDs when a reset signal is input to the multi-processor system to initialize it. Thus, all the microprocessors of the system can be simultaneously started up when the reset signal is disabled. Accordingly, a resetting process in the multi-processor system is simplified, a period of time required for starting up the microprocessor is reduced, and the multi-processor system is easily designed.
    • 提供了适用于构造多处理器系统的微处理器和用于控制微处理器的复位和处理器ID的方法。 微处理器包括解码器,其接收具有预定二进制值的复位ID和复位信号,并对复位ID进行解码; ID生成器接收解码器的解码结果,并生成至少一个微处理器ID和与微处理器串行连接的微处理器的复位ID 微处理器和复位向量单元根据解码器的解码结果来选择复位向量。 多处理器系统被构造成使得当复位信号被输入到多处理器系统以初始化时,系统的独立微处理器分别产生它们自己的复位向量和处理器ID。 因此,当复位信号被禁止时,系统的所有微处理器都可以同时启动。 因此,简化了多处理器系统中的复位处理,减少了启动微处理器所需的时间,容易地设计多处理器系统。