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31. 发明申请

US20160092384A1 READ WRITEABLE RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY MODULES 有权
标题翻译：读取可写入随机可访问的非易失性存储器模块
公开(公告)号：US20160092384A1
公开(公告)日：2016-03-31
申请号：US14499211
申请日：2014-09-28
申请人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
发明人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
IPC分类号： G06F13/28 , G06F12/02 , G06F13/16 , G06F13/40
CPC分类号： G06F13/287 , G06F12/0246 , G06F13/1673 , G06F13/4022 , G06F13/4068 , G06F2212/7203 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices.
摘要翻译：读可写随机可访问的非易失性存储器模块包括具有可插入印刷电路板的插座中的边缘连接器的印刷电路板。读可写随机可访问的非易失性存储器模块还包括多个可读可写非易失性存储器件。

32. 发明授权

US08943245B2 Non-volatile type memory modules for main memory 有权
标题翻译：用于主存储器的非易失性存储模块
公开(公告)号：US08943245B2
公开(公告)日：2015-01-27
申请号：US13747424
申请日：2013-01-22
申请人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
发明人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
IPC分类号： G06F13/12 , G06F12/00
CPC分类号： G06F13/12 , Y02D10/14
摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces.The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
摘要翻译：公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控制器。多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。存储器控制器控制对非易失性存储器模块的读取和写入访问。存储器插座通过印刷电路板迹线耦合到处理器插座。用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。

33. 发明授权

US08782373B2 Seamless application access to hybrid main memory 有权
标题翻译：无缝应用访问混合主存
公开(公告)号：US08782373B2
公开(公告)日：2014-07-15
申请号：US13525960
申请日：2012-06-18
申请人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
IPC分类号： G06F12/00 , G06F3/06 , G06F12/10 , G06F12/14 , G06F13/16
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.
摘要翻译：接收来自应用程序的命令以访问与映射到主存储器的一个或多个虚拟地址相关联的数据结构。识别具有映射到对称存储器组件的组成地址的数据结构的虚拟地址的第一子集以及具有映射到非对称存储器组件的组成地址的数据结构的虚拟地址的第二子集。访问与来自第一物理地址的虚拟地址相关联的数据和与来自第二物理地址的虚拟地址相关联的数据。与对称和非对称存储器组件相关联的数据被应用程序访问，而不向应用程序提供在对称存储器组件或非对称存储器组件内是否访问数据的指示。

34. 发明授权

US08639910B2 Handling writes to a memory including asymmetric and symmetric components 有权
标题翻译：处理对存储器的写入，包括不对称和对称分量
公开(公告)号：US08639910B2
公开(公告)日：2014-01-28
申请号：US13608937
申请日：2012-09-10
申请人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.
摘要翻译：存储器控制器写入与驻留在计算机系统内的主存储器的非对称存储器组件内的数据相关联的虚拟地址，并且具有对称存储器组件，同时保留驻留在非对称存储器组件内的邻近其他数据。计算机系统的主存储器内的对称存储器组件被配置为实现随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块内的其他地址的可用性写这个地址。非对称存储器组件被配置为启用块写入操作，其中对非对称存储器组件的区域内的地址的写入在涉及地址的块写入操作期间影响非对称存储器组件的区域内的其他地址的可用性。

35. 发明授权

US08463993B2 Translating memory modules for main memory 有权
标题翻译：翻译主内存的内存模块
公开(公告)号：US08463993B2
公开(公告)日：2013-06-11
申请号：US13311534
申请日：2011-12-05
申请人： Kenneth Alan Okin , George Moussa , Kumar Ganapathy , Vijay Karamcheti , Rajesh Parekh
发明人： Kenneth Alan Okin , George Moussa , Kumar Ganapathy , Vijay Karamcheti , Rajesh Parekh
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F13/1668 , G06F2212/205 , Y02D10/14
摘要： A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.
摘要翻译：公开了一种翻译存储器模块，其包括印刷电路板，耦合到印刷电路板的至少一个存储器集成电路以及耦合到印刷电路板并耦合在边缘连接器和至少一个存储器集成电路之间的至少一个支撑芯片。所述至少一个支持芯片包括用于在用于所述至少一个存储器集成电路的第一存储器通信协议和用于不同于所述第一存储器通信协议的存储器通道的第二存储器通信协议之间转换的双向转换器。第二存储器通信协议，用于通过存储器通道总线传送数据，地址和控制信号，以将数据读取和写入到转换存储器模块的存储器中。

36. 发明申请

US20130138874A1 SYSTEMS WITH PROGRAMMABLE HETEROGENEOUS MEMORY CONTROLLERS FOR MAIN MEMORY 有权
标题翻译：具有可编程异构存储器控制器的系统用于主存储器
公开(公告)号：US20130138874A1
公开(公告)日：2013-05-30
申请号：US13750811
申请日：2013-01-25
申请人： Kenneth Alan Okin , George Moussa , Kumar Ganapathy , Vijay Karamcheti , Rajesh Parekh
发明人： Kenneth Alan Okin , George Moussa , Kumar Ganapathy , Vijay Karamcheti , Rajesh Parekh
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F13/1668 , G06F2212/205 , Y02D10/14
摘要： A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.
摘要翻译：公开了一种翻译存储器模块，其包括印刷电路板，耦合到印刷电路板的至少一个存储器集成电路以及耦合到印刷电路板并耦合在边缘连接器和至少一个存储器集成电路之间的至少一个支撑芯片。所述至少一个支持芯片包括用于在用于所述至少一个存储器集成电路的第一存储器通信协议和用于不同于所述第一存储器通信协议的存储器通道的第二存储器通信协议之间转换的双向转换器。第二存储器通信协议，用于通过存储器通道总线传送数据，地址和控制信号，以将数据读取和写入到转换存储器模块的存储器中。

37. 发明授权

US08380898B2 Methods for main memory with non-volatile type memory modules 有权
标题翻译：具有非易失性存储器模块的主存储器的方法
公开(公告)号：US08380898B2
公开(公告)日：2013-02-19
申请号：US12832409
申请日：2010-07-08
申请人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
发明人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
IPC分类号： G06F13/12
CPC分类号： G06F13/4009 , G06F12/0638 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
摘要翻译：公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控制器。多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。存储器控制器控制对非易失性存储器模块的读取和写入访问。存储器插座通过印刷电路板迹线耦合到处理器插座。用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。

38. 发明申请

US20120260030A1 SEAMLESS APPLICATION ACCESS TO HYBRID MAIN MEMORY 有权
标题翻译：无缝应用访问混合主存储器
公开(公告)号：US20120260030A1
公开(公告)日：2012-10-11
申请号：US13525960
申请日：2012-06-18
申请人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.
摘要翻译：接收来自应用程序的命令以访问与映射到主存储器的一个或多个虚拟地址相关联的数据结构。识别具有映射到对称存储器组件的组成地址的数据结构的虚拟地址的第一子集以及具有映射到非对称存储器组件的组成地址的数据结构的虚拟地址的第二子集。访问与来自第一物理地址的虚拟地址相关联的数据和与来自第二物理地址的虚拟地址相关联的数据。与对称和非对称存储器组件相关联的数据被应用程序访问，而不向应用程序提供在对称存储器组件或非对称存储器组件内是否访问数据的指示。

39. 发明申请

US20120079181A1 TRANSLATING MEMORY MODULES FOR MAIN MEMORY 有权
标题翻译：转换主存储器的存储器模块
公开(公告)号：US20120079181A1
公开(公告)日：2012-03-29
申请号：US13311534
申请日：2011-12-05
申请人： Kenneth A. Okin , George Moussa , Kumar Ganapathy , Vijay Karamcheti , Rajesh Parekh
发明人： Kenneth A. Okin , George Moussa , Kumar Ganapathy , Vijay Karamcheti , Rajesh Parekh
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F13/1668 , G06F2212/205 , Y02D10/14
摘要： A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.
摘要翻译：公开了一种翻译存储器模块，其包括印刷电路板，耦合到印刷电路板的至少一个存储器集成电路以及耦合到印刷电路板并耦合在边缘连接器和至少一个存储器集成电路之间的至少一个支撑芯片。所述至少一个支持芯片包括用于在用于所述至少一个存储器集成电路的第一存储器通信协议和用于不同于所述第一存储器通信协议的存储器通道的第二存储器通信协议之间转换的双向转换器。第二存储器通信协议，用于通过存储器通道总线传送数据，地址和控制信号，以将数据读取和写入到转换存储器模块的存储器中。

40. 发明授权

US07913055B2 Seamless application access to hybrid main memory 有权
标题翻译：无缝应用访问混合主存
公开(公告)号：US07913055B2
公开(公告)日：2011-03-22
申请号：US11935254
申请日：2007-11-05
申请人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.
摘要翻译：接收来自应用程序的命令以访问与映射到主存储器的一个或多个虚拟地址相关联的数据结构。识别具有映射到对称存储器组件的组成地址的数据结构的虚拟地址的第一子集以及具有映射到非对称存储器组件的组成地址的数据结构的虚拟地址的第二子集。访问与来自第一物理地址的虚拟地址相关联的数据和与来自第二物理地址的虚拟地址相关联的数据。与对称和非对称存储器组件相关联的数据被应用程序访问，而不向应用程序提供在对称存储器组件或非对称存储器组件内是否访问数据的指示。

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