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31. 发明授权

US08493849B2 Systems and methods for creating, managing and communicating users and applications on spontaneous area networks 有权
公开(公告)号：US08493849B2
公开(公告)日：2013-07-23
申请号：US12704904
申请日：2010-02-12
申请人： David Fuste Vilella , Jorge Garcia Vidal , Daniel Nemirovsky , Mario Nemirovsky
发明人： David Fuste Vilella , Jorge Garcia Vidal , Daniel Nemirovsky , Mario Nemirovsky
IPC分类号： H04J1/16 , H04J3/14
CPC分类号： H04L45/02 , H04W40/00 , H04W84/12 , H04W84/18
摘要： A Spontaneous Area Network (SPAN) is formed by mobile and fixed nodes using wireless transmission links between nodes, usually in a nearby geographical area. Applications allow users to create, join, leave, and manage SPANs and groups in a SPAN. Automatic procedures allow nodes to join other SPANs. Transmission power of the wireless network interface is dynamic, varying depending on battery level, type of information to transmit, state and topology of the network. A delay tolerant object layer abstraction creates, modifies, deletes, publishes, and handles Delay Tolerant Distributed Objects (DTDOs). A Patient Transport Protocol (PTP) ensures a reliable transport of information through the network while avoiding congestion conditions. An aggressive and explosive network protocol (AGENET) has routing and forwarding capacities and uses datagrams to establish communication between different nodes of the SPAN. Cooperation and diversity are exploited to react to node mobility that causes frequent changes in network topology and disconnections.

32. 发明申请

US20070260852A1 FETCH AND DISPATCH DISASSOCIATION APPARATUS FOR MULTI-STREAMING PROCESSORS 有权
标题翻译：多流程处理器的FETCH和DISPATCH分配设备
公开(公告)号：US20070260852A1
公开(公告)日：2007-11-08
申请号：US11539322
申请日：2006-10-06
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enrique Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enrique Musoll
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.
摘要翻译：流水线多流处理器具有指令源，从指令源获取指令的多个流，用于向一组执行单元选择和分派指令的调度阶段，具有与多个中的每个流相关联的一个队列的一组指令队列的流，并且位于指令高速缓存和调度阶段之间的流水线中，以及用于在每个周期中选择流以从指令高速缓存获取指令的选择系统。处理器的特征在于，选择系统在每个周期中选择一个或多个流，用于从指令高速缓存取出指令，并且在每个周期中为其取指令的流的数量少于流数在多个流中。

33. 发明申请

US20070256079A1 CONTEXT SELECTION AND ACTIVATION MECHANISM FOR ACTIVATING ONE OF A GROUP OF INACTIVE CONTEXTS IN A PROCESSOR CORE FOR SERVICING INTERRUPTS 有权
标题翻译：用于在一个处理器核心中激活一组不活动内容的服务中断的背景选择和激活机制
公开(公告)号：US20070256079A1
公开(公告)日：2007-11-01
申请号：US11566870
申请日：2006-12-05
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： G06F9/46
CPC分类号： G06F9/461 , G06F9/4812 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, a first determination logic for determining control status of all of the contexts, a second determination logic for determining if a context is idle or not, a selection logic for selecting a context and a context release mechanism for releasing the selected context. Determination by the logic system that all contexts are singularly owned by an entity not responsible for packet processing and that at least one of the contexts is idle, triggers immediate selection and release of an idle one of the at least one idle contexts to an entity responsible for packet processing.
摘要翻译：提供数据分组处理器中的逻辑系统用于选择和释放多个上下文中的一个。所选择和发布的上下文专用于使得能够处理对应于在数据分组处理中生成的中断并且待服务的中断服务例程。该系统包括用于确定所有上下文的控制状态的第一确定逻辑，用于确定上下文是否空闲的第二确定逻辑，用于选择上下文的选择逻辑和用于释放所选择的上下文的上下文释放机制。由逻辑系统确定所有上下文由不对分组处理负责的实体单独拥有，并且至少一个上下文是空闲的，触发所述至少一个空闲上下文中空闲的一个空闲上下文到负责的实体用于数据包处理。

34. 发明授权

US07257814B1 Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors 有权
标题翻译：用于在动态多流处理器中实现存储器操作的原子性的方法和装置
公开(公告)号：US07257814B1
公开(公告)日：2007-08-14
申请号：US09592106
申请日：2000-06-12
申请人： Stephen Melvin , Mario Nemirovsky
发明人： Stephen Melvin , Mario Nemirovsky
IPC分类号： G06F9/00 , G06F7/38 , G06F13/28 , G06F12/00
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087
摘要： A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and a lock mechanism for locking selected memory locations shared by streams of the processor, the hardware-lock mechanism operating to set a lock when an atomic memory sequence is started and to clear a lock when an atomic memory sequence is completed. In preferred embodiments the lock mechanism comprises one or more storage locations associated with each stream of the processor, each storage location enabled to store a memory address a lock bit, and a stall bit. Methods for practicing the invention using the apparatus are also taught.
摘要翻译：多流处理器具有用于流式传输一个或多个指令线程的多个流，用于处理来自流的指令的一组功能资源，以及用于锁定由处理器的流共享的所选择的存储器位置的锁定机构，硬件锁定机构操作在原子存储器序列启动时设置锁定，并且当原子存储器序列完成时清除锁定。在优选实施例中，锁定机构包括与处理器的每个流相关联的一个或多个存储位置，每个存储位置能够存储存储器地址锁定位和失速位。还教导了使用该装置实施本发明的方法。

35. 发明申请

US20070110090A1 METHOD AND APPARATUS FOR OVERFLOWING DATA PACKETS TO A SOFTWARE-CONTROLLED MEMORY WHEN THEY DO NOT FIT INTO A HARDWARE-CONTROLLED MEMORY 有权
标题翻译：将数据分组覆盖到不受硬件控制的存储器中的软件控制的存储器的方法和装置
公开(公告)号：US20070110090A1
公开(公告)日：2007-05-17
申请号：US11552764
申请日：2006-10-25
申请人： Enrique Musoll , Stephen Melvin , Mario Nemirovsky
发明人： Enrique Musoll , Stephen Melvin , Mario Nemirovsky
IPC分类号： H04L12/54
CPC分类号： H04L49/9047 , G06F12/023 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L49/9078 , Y10S707/99953 , Y10S707/99956
摘要： A system for managing packets incoming to a data router has a local packet memory (LPM) mapped into pre-configured memory units, to store packets for processing, an external packet memory (EPM), a first storage system to store packets in the LPM, and a second storage system to store packets in the EPM. The system is characterized in that the first storage system attempts to store all incoming packets in the LPM, and for those packets that are not compatible with the LPM, relinquishes control to the second system, which stores the LPM-incompatible packets in the EPM.
摘要翻译：用于管理进入数据路由器的分组的系统具有映射到预先配置的存储器单元中的本地分组存储器（LPM），以存储用于处理的分组，外部分组存储器（EPM），第一存储系统以在LPM中存储分组以及用于在EPM中存储分组的第二存储系统。该系统的特征在于，第一个存储系统尝试将所有传入的数据包存储在LPM中，对于与LPM不兼容的那些数据包，放弃对EPM中存储LPM不兼容数据包的第二个系统的控制。

36. 发明申请

US20070074014A1 EXTENDED INSTRUCTION SET FOR PACKET PROCESSING APPLICATIONS 审中-公开
标题翻译：扩展的包装处理应用指导
公开(公告)号：US20070074014A1
公开(公告)日：2007-03-29
申请号：US11530945
申请日：2006-09-12
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： G06F7/00
CPC分类号： G06F9/30003 , G06F9/30101 , G06F9/3851 , G06F9/3885 , G06F9/5016 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. The extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit.
摘要翻译：公开了一种用于动态多流处理器的软件程序扩展。该扩展包括能够在分组管理组件和处理器的核心处理组件之间进行协调交互的指令集。该软件程序包括用于管理分组上传和下载进出存储器的部分，其一部分用于管理与排队和出队数据分组相关联的特定存储器分配和去分配，其一部分用于管理多个上下文的使用专用于处理单个数据包; 以及其一部分，用于管理与数据分组处理相关联的算术和其他上下文存储器功能的选择和利用。该扩展补充了用于特定用于具有独立于流处理器单元的分组管理单元的处理器的标准数据分组处理程序体系结构。

37. 发明申请

US20060225080A1 METHODS AND APPARATUS FOR MANAGING A BUFFER OF EVENTS IN THE BACKGROUND 有权
标题翻译：在背景下管理事件缓冲的方法和装置
公开(公告)号：US20060225080A1
公开(公告)日：2006-10-05
申请号：US11278747
申请日：2006-04-05
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F13/126 , G06F2209/544 , G06F2209/546
摘要： A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.
摘要翻译：用于对具有处理器的数据处理系统中的事件进行排序和计费的后台事件缓冲器管理器（BEBM）包括用于从设备接收事件标识（ID）的端口，用于排队接收的事件ID的排队功能和通知功能用于通知处理器排队的事件ID。 BEBM处理处理器的所有事件排序和计费。优选实施例中的BEBM按照类型优先级和类型下的优先级排队事件，并且还处理在对每个事件的处理结束时向设备发送确认，并且缓冲确认过程。在特定实施例中，该装置和方法被教导为分组处理路由器引擎。

38. 发明申请

US20060215670A1 METHOD AND APPARATUS FOR NON-SPECULATIVE PRE-FETCH OPERATION IN DATA PACKET PROCESSING 有权
标题翻译：数据分组处理中非调制型预充电操作的方法和装置
公开(公告)号：US20060215670A1
公开(公告)日：2006-09-28
申请号：US11278890
申请日：2006-04-06
申请人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
发明人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L49/9073 , G06F9/546 , H04L45/00 , H04L45/56 , H04L45/60 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/10 , H04L49/20 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/30 , H04L49/3036 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L69/12
摘要： A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
摘要翻译：提供了一种系统，用于使得能够在分组处理器的即时分组处理之前的后台执行用于处理指令的非推测性预取操作。该系统包括用于接收数据分组并将其排入待处理的分组管理单元，用于处理数据分组的处理器单元，用于保存上下文寄存器的处理器核心存储器和用于处理的功能单元，用于保存多个指令线程的存储器以及用于将队列与指向开始指令线程的指针相关联的软件可配置硬件表。分组管理单元在处理器核心中选择用于处理数据分组的可用上下文，参考表格，并将指针传送到处理器，使得处理器能够对指令进行非推测性预取。

39. 发明申请

US20060159104A1 QUEUEING SYSTEM FOR PROCESSORS IN PACKET ROUTING OPERATIONS 有权
标题翻译：分组路由操作中处理器的队列系统
公开(公告)号：US20060159104A1
公开(公告)日：2006-07-20
申请号：US11277293
申请日：2006-03-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
摘要翻译：在数据包处理器中，在处理期间用于分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动已识别分组的处理，完成的分组的下载或用于重新选择所选分组标识符的选择逻辑。

40. 发明授权

US07035997B1 Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors 有权
标题翻译：用于改进多线程处理器中指令提取和调度的方法和设备
公开(公告)号：US07035997B1
公开(公告)日：2006-04-25
申请号：US09616385
申请日：2000-07-14
申请人： Enric Musoll , Mario Nemirovsky
发明人： Enric Musoll , Mario Nemirovsky
IPC分类号： G06F9/00
CPC分类号： G06F9/3844 , G06F9/3802 , G06F9/3851
摘要： In a multi-streaming processor, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and one or more predictors for forecasting whether a load instruction will hit or miss the cache or a branch will be taken. The prediction or predictions are used by the fetch algorithm in determining from which stream to fetch. In some cases probabilities are determined and also used in decisions, and predictors may be used at either or both of fetch and dispatch stages.
摘要翻译：在多流处理器中，提供用于从多个流中的各个流到指令流水线获取指令的系统，包括用于从哪个流中取出指令的提取算法，以及用于预测加载指令的一个或多个预测器将击中或错过缓存或分支将被采取。提取算法使用预测或预测来确定从哪个流获取。在某些情况下，确定概率并且也用于决策，并且预测器可以在获取和调度阶段中的任一个或两者使用。

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