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31. 发明授权

US08156288B2 Asymmetric memory migration in hybrid main memory 有权
标题翻译：混合主存储器中的非对称存储器迁移
公开(公告)号：US08156288B2
公开(公告)日：2012-04-10
申请号：US12853135
申请日：2010-08-09
申请人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
IPC分类号： G06F13/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.
摘要翻译：通过接收来自应用程序的命令来读取与映射到主存储器的虚拟地址相关联的数据来管理主存储器。存储器控制器确定虚拟地址被映射到主存储器的对称存储器组件中的一个，并且访问指示如何与虚拟地址相关联的数据被访问的存储器使用特性。存储器控制器确定与虚拟地址具有适合于主存储器的非对称存储器组件的访问特征，并将与虚拟地址相关联的数据加载到主存储器的非对称存储器组件。在加载和使用存储器管理单元之后，从应用程序接收到用于读取与虚拟地址相关联的数据的命令，并且从非对称存储器组件检索与虚拟地址相关联的数据。

32. 发明授权

US07970961B2 Method and apparatus for distributed direct memory access for systems on chip 有权
标题翻译：芯片上系统的分布式直接存储器存取方法和装置
公开(公告)号：US07970961B2
公开(公告)日：2011-06-28
申请号：US12268604
申请日：2008-11-11
申请人： Kumar Ganapathy , Ruban Kanapathippillai , Saurin Shah , George Moussa , Earle F. Philhower, III , Ruchir Shah
发明人： Kumar Ganapathy , Ruban Kanapathippillai , Saurin Shah , George Moussa , Earle F. Philhower, III , Ruchir Shah
IPC分类号： G06F13/28 , G06F12/00 , G06F13/36 , G06F15/00
CPC分类号： H04L49/90 , G06F12/08 , G06F13/28 , G06F2213/0038 , G11C7/1072
摘要： A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.
摘要翻译：在片上系统（SOC）中提供分布式直接存储器访问（DMA）方法，装置和系统。 DMA控制器单元被分配到各种需要直接存储器访问的功能模块。功能模块与直接存储器访问发生的系统总线接口。将期望直接存储器访问的全局缓冲存储器耦合到系统总线。总线仲裁器用于仲裁哪些功能模块可以访问系统总线来执行直接存储器访问。一旦由总线仲裁器选择功能模块来访问系统总线，就可以建立与全局缓冲存储器的DMA程序。

33. 发明申请

US20100274959A1 METHODS FOR MAIN MEMORY WITH NON-VOLATILE TYPE MEMORY MODULES 有权
标题翻译：具有非易失型存储器模块的主存储器的方法
公开(公告)号：US20100274959A1
公开(公告)日：2010-10-28
申请号：US12832409
申请日：2010-07-08
申请人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
发明人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
IPC分类号： G06F12/00 , G06F12/02 , G06F17/30
CPC分类号： G06F13/4009 , G06F12/0638 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
摘要翻译：公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控制器。多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。存储器控制器控制对非易失性存储器模块的读取和写入访问。存储器插座通过印刷电路板迹线耦合到处理器插座。用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。

34. 发明申请

US20090210636A1 METHODS AND SYSTEMS FOR TWO-DIMENSIONAL MAIN MEMORY 有权
标题翻译：二维主记忆的方法和系统
公开(公告)号：US20090210636A1
公开(公告)日：2009-08-20
申请号：US12369728
申请日：2009-02-11
申请人： Vijay Karamcheti , Kumar Ganapathy
发明人： Vijay Karamcheti , Kumar Ganapathy
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C5/04 , G11C29/76
摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
摘要翻译：在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。存储器模块的多个存储器片段中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。从存储器控制器从地址控制器接收存储器模块的存储器访问请求。从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

35. 发明申请

US20080109629A1 ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY 有权
标题翻译：混合主存储器中的不对称存储器迁移
公开(公告)号：US20080109629A1
公开(公告)日：2008-05-08
申请号：US11935224
申请日：2007-11-05
申请人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.
摘要翻译：通过接收来自应用程序的命令来读取与映射到主存储器的虚拟地址相关联的数据来管理主存储器。存储器控制器确定虚拟地址被映射到主存储器的对称存储器组件中的一个，并且访问指示如何与虚拟地址相关联的数据被访问的存储器使用特性。存储器控制器确定与虚拟地址具有适合于主存储器的非对称存储器组件的访问特征，并将与虚拟地址相关联的数据加载到主存储器的非对称存储器组件。在加载和使用存储器管理单元之后，从应用程序接收到用于读取与虚拟地址相关联的数据的命令，并且从非对称存储器组件检索与虚拟地址相关联的数据。

36. 发明授权

US07233166B2 Bus state keepers 失效
标题翻译：巴士守门员
公开(公告)号：US07233166B2
公开(公告)日：2007-06-19
申请号：US10649067
申请日：2003-08-27
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
IPC分类号： H03K19/003 , H03K17/16 , G11C27/02
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in response to a select signal.
摘要翻译：总线状态保持者保持不活动的公共汽车的稳定状态以节省电力。在本发明的一个实施例中，总线状态保持器包括多个复用器和多个触发器。多个触发器响应于选择信号来存储总线的状态。

37. 发明授权

US06772319B2 Dyadic instruction processing instruction set architecture with 20-bit and 40-bit DSP and control instructions 失效
标题翻译：具有20位和40位DSP的二进制指令处理指令集架构和控制指令
公开(公告)号：US06772319B2
公开(公告)日：2004-08-03
申请号：US10215721
申请日：2002-08-08
申请人： Kumar Ganapathy , Ruban Kanapathipillai
发明人： Kumar Ganapathy , Ruban Kanapathipillai
IPC分类号： G06F9302
CPC分类号： G06F9/3877 , G06F9/3001 , G06F9/30072 , G06F9/30149 , G06F9/30189 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3885 , G06F15/8015
摘要： An instruction set architecture (ISA) to convert voice and data samples into packets for transmission over a network and to convert packets received from the network into voice and data samples. In one embodiment, the ISA includes a digital signal processing (DSP) instruction set architecture for a plurality of signal processing units and a control instruction set architecture to control the execution of DSP instructions by the plurality of signal processing units. In another embodiment, the ISA includes a plurality of DSP instructions including a 20-bit DSP instruction and a 40-bit DSP instruction and a plurality of control instructions to control execution of the plurality of DSP instructions including a 20-bit control instruction and a 40-bit control instruction. The DSP instructions may be dyadic DSP instructions including a main DSP operation and a sub DSP operation.
摘要翻译：一种指令集架构（ISA），用于将语音和数据样本转换成分组，用于通过网络进行传输，并将从网络接收的数据包转换为语音和数据样本。在一个实施例中，ISA包括用于多个信号处理单元的数字信号处理（DSP）指令集架构和用于控制由多个信号处理单元执行DSP指令的控制指令集架构。在另一个实施例中，ISA包括多个DSP指令，包括20位DSP指令和40位DSP指令以及多个控制指令，以控制多个DSP指令的执行，包括20位控制指令和 40位控制指令。 DSP指令可以是二进制DSP指令，包括主DSP操作和子DSP操作。

38. 发明授权

US06631461B2 Dyadic DSP instructions for digital signal processors 失效
公开(公告)号：US06631461B2
公开(公告)日：2003-10-07
申请号：US10216575
申请日：2002-08-08
申请人： Kumar Ganapathy , Ruban Kanapathipillai
发明人： Kumar Ganapathy , Ruban Kanapathipillai
IPC分类号： G06F9302
CPC分类号： G06F9/3877 , G06F9/3001 , G06F9/30072 , G06F9/30149 , G06F9/30189 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3885 , G06F15/8015
摘要： An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

39. 发明申请

US20160092384A1 READ WRITEABLE RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY MODULES 有权
标题翻译：读取可写入随机可访问的非易失性存储器模块
公开(公告)号：US20160092384A1
公开(公告)日：2016-03-31
申请号：US14499211
申请日：2014-09-28
申请人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
发明人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
IPC分类号： G06F13/28 , G06F12/02 , G06F13/16 , G06F13/40
CPC分类号： G06F13/287 , G06F12/0246 , G06F13/1673 , G06F13/4022 , G06F13/4068 , G06F2212/7203 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices.
摘要翻译：读可写随机可访问的非易失性存储器模块包括具有可插入印刷电路板的插座中的边缘连接器的印刷电路板。读可写随机可访问的非易失性存储器模块还包括多个可读可写非易失性存储器件。

40. 发明授权

US08943245B2 Non-volatile type memory modules for main memory 有权
标题翻译：用于主存储器的非易失性存储模块
公开(公告)号：US08943245B2
公开(公告)日：2015-01-27
申请号：US13747424
申请日：2013-01-22
申请人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
发明人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
IPC分类号： G06F13/12 , G06F12/00
CPC分类号： G06F13/12 , Y02D10/14
摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces.The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
摘要翻译：公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控制器。多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。存储器控制器控制对非易失性存储器模块的读取和写入访问。存储器插座通过印刷电路板迹线耦合到处理器插座。用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。

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