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31. 发明授权

US06738310B2 Nonvolatile semiconductor memory 失效
公开(公告)号：US06738310B2
公开(公告)日：2004-05-18
申请号：US10351524
申请日：2003-01-27
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C700
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

32. 发明授权

US06538912B2 Semiconductor device 有权
公开(公告)号：US06538912B2
公开(公告)日：2003-03-25
申请号：US10139330
申请日：2002-05-07
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

33. 发明授权

US06400596B2 Semiconductor memory device using open data line arrangement 有权
标题翻译：半导体存储器件采用开放数据线布置
公开(公告)号：US06400596B2
公开(公告)日：2002-06-04
申请号：US09725107
申请日：2000-11-29
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.
摘要翻译：当使用相移方法作为光刻技术时，将读出放大器交替放置在能够实现DRAM面积减小的一个交叉点存储器中，难以在读出放大器与每个读出放大器之间的边界区域中布置数据线内存阵列因此，提供了根据本发明的半导体器件。在半导体器件中，在副存储器阵列内或插入其间的两条数据线被连接到相邻的读出放大器，作为用于当读出放大器交替地从子存储器阵列（SMA）到读出放大器（SA）的数据线绘制的系统放置即，分别连接到两个相邻读出放大器的数据线之间的数据线的数目被设置为偶数（0,2,4 ...）。由于上述结构，可以避免在读出放大器块和子存储器阵列连接的部分中的断路和短路，并且便于连接布局。

34. 发明授权

US06281725B1 Semiconductor integrated circuit having a clock recovery circuit 有权
标题翻译：具有时钟恢复电路的半导体集成电路
公开(公告)号：US06281725B1
公开(公告)日：2001-08-28
申请号：US09337421
申请日：1999-06-22
申请人： Satoru Hanzawa , Takeshi Sakata , Katsutaka Kimura
发明人： Satoru Hanzawa , Takeshi Sakata , Katsutaka Kimura
IPC分类号： H03L700
CPC分类号： H03K5/135 , H03K5/133 , H03L7/0814 , H03L7/0818 , H04L7/0008
摘要： A clock recovery circuit is provided for use in a memory with a clock synchronized interface or the like, wherein an external clock is temporarily intercepted to shorten the lock-in time when an internal clock is to be generated from the external clock. The clock recovery circuit includes a delay circuit array, into which an external clock is inputted, for generating a plurality of reference clocks, a control circuit for comparing the phases of the external clock and of the plurality of reference clocks and detecting the number of delay stages of the delay circuits required for locking in, and latching circuit for holding the number of delay stages required for locking in. Once synchronism is detected and the number of delay stages required for locking in are held in the latching circuit, the generation of the internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.
摘要翻译：提供了一种用于具有时钟同步接口等的存储器中的时钟恢复电路，其中暂时截取外部时钟以缩短当从外部时钟产生内部时钟时的锁定时间。时钟恢复电路包括：输入外部时钟的延迟电路阵列，用于产生多个参考时钟;控制电路，用于比较外部时钟和多个参考时钟的相位，并且检测所述多个参考时钟的延迟级数锁定所需的延迟电路和用于保持锁定所需的延迟级数的锁存电路。一旦检测到同步，锁定所需的延迟级数被保持在锁存电路中，则产生内部时钟可以即使暂时停止外部时钟的供给，也可以在短时间内恢复。

35. 发明授权

US06272042B1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US06272042B1
公开(公告)日：2001-08-07
申请号：US09630426
申请日：2000-08-01
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C1604
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Each memory cell of a nonvolatile semiconductor memory, essentially, consists of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Furthermore, because the negative voltage applied to the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.
摘要翻译：非易失性半导体存储器的每个存储单元基本上由诸如具有浮置栅电极的MOSFET的单晶体管型存储单元组成。当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。此外，由于施加到字线的负电压，可以降低数据编程时的漏极电压，从而可以减轻沟道部分处的栅极氧化膜的劣化。

36. 发明授权

US6134148A Semiconductor integrated circuit and data processing system 有权
公开(公告)号：US6134148A
公开(公告)日：2000-10-17
申请号：US378505
申请日：1999-08-20
申请人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34 , G11C11/34
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C29/00
摘要： A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

37. 发明授权

US5875347A Neural network processing system using semiconductor memories 失效
标题翻译：使用半导体存储器的神经网络处理系统
公开(公告)号：US5875347A
公开(公告)日：1999-02-23
申请号：US723012
申请日：1996-09-30
申请人： Takao Watanabe , Katsutaka Kimura , Kiyoo Itoh , Yoshiki Kawajiri
发明人： Takao Watanabe , Katsutaka Kimura , Kiyoo Itoh , Yoshiki Kawajiri
IPC分类号： G06F15/18 , G06F17/16 , G06N3/04 , G06N3/063 , G06N99/00 , G06F15/00
CPC分类号： G06N3/063
摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a largescale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.
摘要翻译：这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以实现用于确定诸如乘积或和的中子输出值所需的处理的至少一部分在平行下。此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

38. 发明授权

US5694358A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5694358A
公开(公告)日：1997-12-02
申请号：US706267
申请日：1996-09-24
申请人： Takayuki Kawahara , Yusuke Jyouno , Syunichi Saeki , Naoki Miyamoto , Katsutaka Kimura
发明人： Takayuki Kawahara , Yusuke Jyouno , Syunichi Saeki , Naoki Miyamoto , Katsutaka Kimura
IPC分类号： G11C17/00 , G11C7/18 , G11C16/06 , G11C16/26 , G11C7/00
CPC分类号： G11C16/26 , G11C7/18
摘要： This invention provides a nonvolatile semiconductor memory device having a word line, a plurality of bit lines crossing the word line, and a plurality of memory cells including MOS transistors. Each of control gates of the MOS transistors are coupled to the word line and each of drains thereof are coupled to the bit lines, respectively. Each of the MOS transistors also has a floating gate. Further, the non-volatile semiconductor memory device comprises latch circuits, first switches, a sense amplifier coupled to the plurality of bit lines in common, and second switches. The latch circuits are coupled to the plurality of bit lines through the first switches which are coupled between the plurality of bit lines and the latch circuits, respectively. The second switches are respectively coupled between the plurality of bit lines and the sense amplifier, thereby coupling the sense amplifier to the bit lines. Each of the plurality of first switches includes a MOS transistor whose source-drain path is between a corresponding one of the plurality of bit lines and a corresponding one of the latch circuits, respectively. When data is to be read from a memory cell selected out of the plurality of memory cells, the plurality of first switches are turned off and one of the second switches between the selected memory cell and the sense amplifier is turned on.
摘要翻译：本发明提供一种具有字线，与字线交叉的多个位线以及包括MOS晶体管的多个存储单元的非易失性半导体存储器件。 MOS晶体管的每个控制栅极耦合到字线，并且其每个漏极分别耦合到位线。每个MOS晶体管也具有浮动栅极。此外，非易失性半导体存储器件包括锁存电路，第一开关，共同耦合到多个位线的读出放大器和第二开关。锁存电路通过分别耦合在多个位线和锁存电路之间的第一开关耦合到多个位线。第二开关分别耦合在多个位线和读出放大器之间，从而将读出放大器耦合到位线。多个第一开关中的每一个包括MOS晶体管，其源极 - 漏极路径分别位于多个位线中的相应一个位线和相应的一个锁存电路之间。当要从多个存储单元中选择的存储单元读取数据时，多个第一开关被截止，并且所选存储单元和读出放大器之间的第二开关中的一个导通。

39. 发明授权

US5467314A Method of testing an address multiplexed dynamic RAM 失效
标题翻译：测试地址多路复用动态RAM的方法
公开(公告)号：US5467314A
公开(公告)日：1995-11-14
申请号：US277430
申请日：1994-07-18
申请人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
发明人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
IPC分类号： G11C11/401 , G01R31/317 , G11C29/00 , G11C29/14 , G11C29/46 , G11C7/00
CPC分类号： G11C29/46 , G01R31/31701
摘要： In an address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability, the test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.
摘要翻译：在具有正常操作模式和测试模式能力的地址多路复用动态随机存取存储器（RAM）中，测试模式是响应于行地址选通（＆amp; Upbar＆R）和列地址选通（＆upbar＆C）信号和写使能（＆upbar＆W）信号。由于在动态RAM的正常操作模式中不使用与实现测试模式相关的信号电平组合，因此不需要额外的外部终端。该动态RAM在动态RAM的输入侧和输出侧都采用多路复用电路，该复用电路在正常操作期间通过来自解码器的选择信号以及在测试模式期间通过允许访问的测试信号通过测试电路在所有公共补充数据线上的数据，以便确定正在读出的用于测试的数据是否一致或不一致。

40. 发明授权

US5151772A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5151772A
公开(公告)日：1992-09-29
申请号：US616705
申请日：1990-11-20
申请人： Yasushi Takahashi , Hiromi Matsuura , Yoshihisa Koyama , Masaya Muranaka , Katsutaka Kimura , Kazuyuki Miyazawa , Masamichi Ishihara , Hidetoshi Iwai
发明人： Yasushi Takahashi , Hiromi Matsuura , Yoshihisa Koyama , Masaya Muranaka , Katsutaka Kimura , Kazuyuki Miyazawa , Masamichi Ishihara , Hidetoshi Iwai
IPC分类号： H01L23/522 , H01L27/108
CPC分类号： H01L23/5226 , H01L27/10805 , H01L2924/0002 , Y10S257/923
摘要： A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.
摘要翻译：提供一种半导体集成电路器件，其包括位于半导体衬底的大致中心区域中的存储单元阵列，其具有位于半导体衬底两端的外围电路。还提供了将外围电路彼此耦合的布线层。该布线层被布置成具有彼此电耦合的第一和第二铝层的双层结构。

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