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31. 发明授权

US07071070B2 Method of fabricating capacitor 有权
标题翻译：制造电容器的方法
公开(公告)号：US07071070B2
公开(公告)日：2006-07-04
申请号：US10711533
申请日：2004-09-24
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/20
CPC分类号： H01L21/26586 , H01L27/0805 , H01L28/86 , H01L29/665
摘要： A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a single doped region as a lower electrode in the substrate under the upper electrode.
摘要翻译：描述制造电容器的方法。介电层形成在衬底上。在电介质层上形成有多个开口的上电极。然后，通过开口对衬底进行掺杂步骤，以在上电极下的衬底中形成作为下电极的单一掺杂区域。

32. 发明申请

US20060068559A1 METHOD OF FABRICATING CAPACITOR 有权
标题翻译：制造电容器的方法
公开(公告)号：US20060068559A1
公开(公告)日：2006-03-30
申请号：US10711533
申请日：2004-09-24
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/20 , H01L21/44
CPC分类号： H01L21/26586 , H01L27/0805 , H01L28/86 , H01L29/665
摘要： A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a single doped region as a lower electrode in the substrate under the upper electrode.
摘要翻译：描述制造电容器的方法。介电层形成在衬底上。在电介质层上形成有多个开口的上电极。然后，通过开口对衬底进行掺杂步骤，以在上电极下的衬底中形成作为下电极的单一掺杂区域。

33. 发明申请

US20050151612A1 SYMMETRICAL INDUCTOR 有权
标题翻译：对称电感器
公开(公告)号：US20050151612A1
公开(公告)日：2005-07-14
申请号：US10707771
申请日：2004-01-11
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01F17/00 , H01F27/34 , H01F27/28
CPC分类号： H01F17/0006 , H01F27/34 , H01F2017/0046
摘要： A symmetrical inductor includes a first metal layer, the first metal layer having a first conductive segment disposed on a first side of a line, and a second conductive segment disposed on a second side of the line, the second conductive segment and the first conductive segment being symmetrical to the line; a second metal layer, the second metal layer having a third conductive segment disposed on the first side of the line, and a fourth conductive segment disposed on the second side of the line, the fourth conductive segment and the third conductive segment being symmetrical to the line; a first contact plug for connecting the first conductive segment with a first end of the third conductive segment; a second contact plug for connecting the first conductive segment with a second end of the third conductive segment; a third contact plug for connecting the second conductive segment with a first end of the fourth conductive segment, the third contact plug and the first contact plug being symmetrical to the line; and a fourth contact plug for connecting the second conductive segment with a second end of the fourth conductive segment, the fourth contact plug and the second contact plug being symmetrical to the line.
摘要翻译：对称电感器包括第一金属层，第一金属层具有设置在线的第一侧上的第一导电段和设置在该线的第二侧上的第二导电段，第二导电段和第一导电段与线对称; 第二金属层，所述第二金属层具有设置在所述线的第一侧上的第三导电段，以及设置在所述线的第二侧上的第四导电段，所述第四导电段和所述第三导电段与线; 第一接触插头，用于将第一导电段与第三导电段的第一端连接; 用于将第一导电段与第三导电段的第二端连接的第二接触插塞; 用于将所述第二导电段与所述第四导电段的第一端连接的第三接触插塞，所述第三接触插塞和所述第一接触插塞与所述线对称; 以及用于将所述第二导电段与所述第四导电段的第二端连接的第四接触插塞，所述第四接触插塞和所述第二接触插塞与所述线对称。

34. 发明申请

US20050118778A1 METAL-INSULATOR-METAL (MIM) CAPACITOR AND FABRICATION METHOD FOR MAKING THE SAME 有权
标题翻译：金属绝缘体金属（MIM）电容器及其制造方法
公开(公告)号：US20050118778A1
公开(公告)日：2005-06-02
申请号：US10905472
申请日：2005-01-06
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L23/522 , H01L27/108
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor includes a first metal plate; a first capacitor dielectric layer disposed on the first metal plate and a second metal plate stacked on the first capacitor dielectric layer. The first metal plate, the first capacitor dielectric layer, and the second metal plate constitute a lower capacitor. A second capacitor dielectric layer is disposed on the second metal plate. A third metal plate is stacked on the second capacitor dielectric layer. The second metal plate, the second capacitor dielectric layer, and the third metal plate constitute an upper capacitor. The first metal plate and the third metal plate are electrically connected to a first terminal of the MIM capacitor, while the second metal plate is electrically connected to a second terminal of the MIM capacitor.
摘要翻译：金属绝缘体金属（MIM）电容器包括第一金属板; 设置在第一金属板上的第一电容器介质层和堆叠在第一电容器介电层上的第二金属板。第一金属板，第一电容器电介质层和第二金属板构成下电容器。第二电容器电介质层设置在第二金属板上。第三金属板堆叠在第二电容器介电层上。第二金属板，第二电容器电介质层和第三金属板构成上电容器。第一金属板和第三金属板电连接到MIM电容器的第一端子，而第二金属板电连接到MIM电容器的第二端子。

35. 发明申请

US20050101098A1 METHOD OF FORMING A VARACTOR 有权
标题翻译：形成变量的方法
公开(公告)号：US20050101098A1
公开(公告)日：2005-05-12
申请号：US10605972
申请日：2003-11-11
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/20 , H01L21/322 , H01L21/329 , H01L27/06 , H01L27/08 , H01L29/93
CPC分类号： H01L29/66174 , H01L27/0629 , H01L27/0808 , H01L29/93
摘要： A method of forming a varactor includes forming an ion well of a first conductivity type on a substrate and a plurality of isolation structures on the ion well. The isolation structures define at least an active area on the ion well. Following that, ions of the first conductivity type are implanted into the ion well to form a doping region within the active area. A doping layer of a second conductivity type is then formed on the substrate to cover portions of the doping region. A salicide layer is formed on the doping region and the doping layer.
摘要翻译：形成变容二极管的方法包括在衬底上形成第一导电类型的离子阱和在离子阱上形成多个隔离结构。隔离结构至少限定了离子阱上的有效面积。之后，将第一导电类型的离子注入到离子阱中，以在有源区内形成掺杂区。然后在衬底上形成第二导电类型的掺杂层以覆盖掺杂区域的部分。在掺杂区域和掺杂层上形成自对准硅化物层。

36. 发明授权

US06884689B2 Fabrication of self-aligned bipolar transistor 有权
公开(公告)号：US06884689B2
公开(公告)日：2005-04-26
申请号：US10290635
申请日：2002-11-12
申请人： Shu-Ya Chuang , Jing-Horng Gau , Anchor Chen
发明人： Shu-Ya Chuang , Jing-Horng Gau , Anchor Chen
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/66318
摘要： A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.

37. 发明授权

US06881638B1 Method of fabricating a bipolar junction transistor 失效
标题翻译：制造双极结型晶体管的方法
公开(公告)号：US06881638B1
公开(公告)日：2005-04-19
申请号：US10707215
申请日：2003-11-26
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/331 , H01L29/732
CPC分类号： H01L29/66287 , H01L29/732
摘要： A substrate with a plurality of isolation structures for defining at least an active area thereon is provided. Ions of a first conductive type are implanted into the substrate to form a doping region in the active area. Following that, a protective layer is formed on the substrate, the protective layer having an opening to expose the doping region. A first doping layer of a second conductive type and a second doping layer of the first conductive type are formed on the doping region, respectively, to complete fabrication of a bipolar junction transistor.
摘要翻译：提供了具有用于限定其上的至少一个有效区域的多个隔离结构的衬底。将第一导电类型的离子注入到衬底中以在有源区域中形成掺杂区域。之后，在衬底上形成保护层，保护层具有露出掺杂区的开口。第一导电类型的第一掺杂层和第一导电类型的第二掺杂层分别形成在掺杂区上，以完成双极结型晶体管的制造。

38. 发明授权

US06423597B1 Structure of a DRAM and a manufacturing process thereof 失效
标题翻译： DRAM的结构及其制造方法
公开(公告)号：US06423597B1
公开(公告)日：2002-07-23
申请号：US09767498
申请日：2001-01-23
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10885 , H01L28/84 , H01L28/90
摘要： A structure of a DRAM and a manufacturing process therefor, suitable for a substrate on which a plurality of word lines and a plurality of source/drain regions on sides of each of these word lines are formed. A plurality of bit line contacts and a plurality of node contacts are formed in electric contact with the source/drain regions. A first patterned insulating layer is formed on the substrate, in which a plurality of openings are formed in the insulating layer to expose the bit line contacts. The substrate is covered with a first conductive layer and a second insulating layer in sequence. The second insulating layer, the first conductive layer and the first insulating layer are patterned in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connecting to the bit contacts, exposing the node contacts. As a result, the bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines. A plurality of spacers are formed on sidewalls of the bit line stacked structure. A plurality of second conductive layers are formed conformal to the surfaces of the trenches. The second conductive layers are patterned to form a plurality of bottom electrodes electrically connected to the node contacts.
摘要翻译：一种DRAM的结构及其制造方法，适用于在其上形成有这些字线的每一侧的多个字线和多个源极/漏极区域的基板。多个位线触点和多个节点触点形成为与源/漏区电接触。第一图案化绝缘层形成在基板上，其中在绝缘层中形成多个开口以露出位线触点。衬底被依次覆盖有第一导电层和第二绝缘层。第二绝缘层，第一导电层和第一绝缘层依次图案化以形成多个位线堆叠结构和电连接到位触点的多个位线，露出节点触点。结果，位线堆叠结构形成多个沟槽，并且位线堆叠结构与字线正交。多个间隔件形成在位线堆叠结构的侧壁上。多个第二导电层形成为与沟槽的表面一致。图案化第二导电层以形成电连接到节点触点的多个底部电极。

39. 发明授权

US06329255B1 Method of making self-aligned bit-lines 失效
标题翻译：制作自对准位线的方法
公开(公告)号：US06329255B1
公开(公告)日：2001-12-11
申请号：US09620230
申请日：2000-07-20
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21336
CPC分类号： H01L27/10885 , H01L21/76885 , H01L21/76897 , H01L27/10852 , H01L27/10888
摘要： The present invention provides a method of making self-aligned bit-lines on a substrate, the surface of which comprises a dielectric layer having a plurality of node contact holes and bit-line contact holes. A first conducting layer is formed on the surface of the substrate, filling each node contact hole and bit-line contact hole. Next, a protecting layer is formed over the first conducting layer. The protecting layer and the first conducting layer are etched to form each node contact and bit-line contact. A spacer is formed around each node contact. A second dielectric layer is formed on the wafer, and then etched down to the first dielectric layer and to the surface of each bit-line contact, forming a trench in the second dielectric layer. A second conducting layer is formed on the surface of the substrate, filling each bit-line trench, and a back etching process is performed to remove the second conducting layer from the surface of the second dielectric layer and from each trench down to a certain depth, resulting in a bit-line. Finally, a third dielectric layer is formed on the surface of the substrate, filling each trench.
摘要翻译：本发明提供一种在衬底上制作自对准位线的方法，其表面包括具有多个节点接触孔和位线接触孔的电介质层。在基板的表面上形成第一导电层，填充每个节点接触孔和位线接触孔。接下来，在第一导电层上形成保护层。蚀刻保护层和第一导电层以形成每个节点接触和位线接触。围绕每个节点接触形成间隔物。第二电介质层形成在晶片上，然后蚀刻到第一电介质层和每个位线接触表面，在第二介电层中形成沟槽。在基板的表面上形成第二导电层，填充每个位线沟槽，并执行背蚀刻工艺以从第二介电层的表面和每个沟槽向下移动到一定深度的第二导电层，导致位线。最后，在衬底的表面上形成第三电介质层，填充每个沟槽。

40. 发明授权

US06245625B1 Fabrication method of a self-aligned contact window 失效
标题翻译：自对准接触窗的制作方法
公开(公告)号：US06245625B1
公开(公告)日：2001-06-12
申请号：US09336553
申请日：1999-06-19
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21336
CPC分类号： H01L21/76897
摘要： A method of fabricating a self-aligned contact window structure is described in which a substrate is provided with a plurality of gates formed on the substrate and a plurality of lightly doped regions is formed in the substrate on both sides of the gate. A first dielectric layer of a certain thickness is then formed on the substrate with the surface of the first dielectric layer being lower than the surfaces of the gates such that the sidewalls of the gates are partially exposed. A plurality of spacers is further formed on the exposed sidewalls of the gates. Using the gates and the spacers as masks, the first dielectric layer is anisotropically etched until the lightly doped regions are partially exposed. Using the gate and the spacer as masks, a plurality of heavily doped regions is formed in the lightly doped region and in the substrate. A second dielectric layer is formed covering the gates. The second dielectric is then defined to form a self-aligned contact window.
摘要翻译：描述了一种制造自对准接触窗结构的方法，其中衬底设置有形成在衬底上的多个栅极，并且在栅极两侧的衬底中形成多个轻掺杂区域。然后在衬底上形成一定厚度的第一电介质层，其中第一介电层的表面低于栅极的表面，使得栅极的侧壁部分露出。在栅极的暴露的侧壁上进一步形成多个间隔物。使用栅极和间隔物作为掩模，第一介电层被各向异性蚀刻，直到轻掺杂区域部分暴露。使用栅极和间隔物作为掩模，在轻掺杂区域和衬底中形成多个重掺杂区域。形成覆盖栅极的第二电介质层。然后限定第二电介质以形成自对准的接触窗口。

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