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31. 发明申请

US20100248460A1 Method of forming information storage pattern 审中-公开
标题翻译：形成信息存储模式的方法
公开(公告)号：US20100248460A1
公开(公告)日：2010-09-30
申请号：US12659959
申请日：2010-03-26
申请人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Jung-Hyeon Kim
发明人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Jung-Hyeon Kim
IPC分类号： H01L21/365 , H01L21/469 , H01L21/443 , H01L21/465
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1616 , H01L45/1683
摘要： A method of forming an information storage pattern, includes placing a semiconductor substrate in a process chamber, injecting first, second and third process gases into the process chamber during a first process to form a lower layer on the substrate based on a first injection time and/or a first pause time, injecting the second process gas into the process chamber during a second process, wherein the second process gas is injected into the process chamber during a first elimination time, injecting a fourth process gas together with the second and third process gases into the process chamber during a third process in accordance with a second injection time and/or a second pause time to form an upper layer on the lower layer, and injecting the second process gas into the process chamber during a fourth process, wherein the second process gas is injected into the process chamber during a second elimination.
摘要翻译：一种形成信息存储图案的方法，包括将半导体衬底放置在处理室中，在第一过程中将第一，第二和第三处理气体注入到处理室中，以在第一注入时间基底上形成下层;以及 /或第一暂停时间，在第二过程期间将第二处理气体注入处理室，其中第二处理气体在第一消除时间期间被注入到处理室中，与第二和第三处理一起喷射第四处理气体根据第二喷射时间和/或第二暂停时间，在第三过程期间将气体进入处理室，以在下层形成上层，并且在第四过程期间将第二处理气体注入到处理室中，其中，在第二次消除期间将第二工艺气体注入到处理室中。

32. 发明申请

US20100248442A1 METHODS OF FORMING A PHASE CHANGE MEMORY DEVICE 有权
标题翻译：形成相变存储器件的方法
公开(公告)号：US20100248442A1
公开(公告)日：2010-09-30
申请号：US12731637
申请日：2010-03-25
申请人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Young-Lim Park , Jung-Hyeon Kim
发明人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Young-Lim Park , Jung-Hyeon Kim
IPC分类号： H01L21/02
CPC分类号： H01L45/1616 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.
摘要翻译：提供形成相变存储器件的方法。可以制备具有下电极和层间绝缘层的半导体器件。下电极可以被层间绝缘层包围。可以将源气体，反应气体和吹扫气体注入到半导体制造装置的处理室中，以在半导体衬底上形成相变材料层。源气体可以同时注入到处理室中。相变材料层可以通过层间绝缘层与下电极接触。可以蚀刻相变材料层以在层间绝缘层中形成相变存储单元。可以在相变存储单元上形成上电极。

33. 发明授权

US07767568B2 Phase change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07767568B2
公开(公告)日：2010-08-03
申请号：US11905244
申请日：2007-09-28
申请人： Hyeong-Geun An , Hideki Horii , Jong-Chan Shin , Dong-Ho Ahn , Jun-Soo Bae , Jeong-Hee Park
发明人： Hyeong-Geun An , Hideki Horii , Jong-Chan Shin , Dong-Ho Ahn , Jun-Soo Bae , Jeong-Hee Park
IPC分类号： H01L21/3205
CPC分类号： H01L27/2463 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1683
摘要： A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane.
摘要翻译：提供了一种相变存储器件及其制造方法。具有第一表面的第一电极设置在基板上。具有与第一表面不同的第二表面的第二电极在基板上。第二电极可以与第一电极间隔开。可以对应于第一电极形成第三电极。可以对应于第二电极形成第四电极。可以在第一表面和第三电极之间插入第一相变图案。可以在第二表面和第四电极之间插入第二相变图案。第一和第二相变图案的上表面可以在同一平面上。

34. 发明申请

US20100093130A1 Methods of forming multi-level cell of semiconductor memory 有权
标题翻译：形成半导体存储器多级单元的方法
公开(公告)号：US20100093130A1
公开(公告)日：2010-04-15
申请号：US12587772
申请日：2009-10-13
申请人： Gyu-Hwan Oh , Hyeong-Geun An , Soon-Oh Park , Dong-Ho Ahn , Young-Lim Park
发明人： Gyu-Hwan Oh , Hyeong-Geun An , Soon-Oh Park , Dong-Ho Ahn , Young-Lim Park
IPC分类号： H01L21/06
CPC分类号： H01L45/141 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/1666 , H01L45/1683
摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.
摘要翻译：提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能在设置和复位状态下存储。此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此可以实现四个或更多个不同的电阻。

35. 发明申请

US20090243117A1 CONTACT STRUCTURE, A SEMICONDUCTOR DEVICE EMPLOYING THE SAME, AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：接触结构，使用其的半导体器件及其制造方法
公开(公告)号：US20090243117A1
公开(公告)日：2009-10-01
申请号：US12412657
申请日：2009-03-27
申请人： Jeong-Hee Park , Yong-Ho Ha , Hyeong-Geun An , Joon-Sang Park , Hyun-Suk Kwon , Myung-Jin Kang , Doo-Hwan Park
发明人： Jeong-Hee Park , Yong-Ho Ha , Hyeong-Geun An , Joon-Sang Park , Hyun-Suk Kwon , Myung-Jin Kang , Doo-Hwan Park
IPC分类号： H01L23/522 , H05K1/11
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1666
摘要： A contact structure that includes a first pattern formed on a substrate, wherein the first pattern has a recessed region in an upper surface thereof, a planarized buffer pattern formed on the first pattern, and a conductive pattern formed on the planarized buffer pattern.
摘要翻译：一种接触结构，其包括形成在基板上的第一图案，其中所述第一图案在其上表面具有凹陷区域，形成在所述第一图案上的平坦化缓冲图案，以及形成在所述平坦化缓冲图案上的导电图案。

36. 发明申请

US20080093590A1 Phase change memory device and method of forming the same 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20080093590A1
公开(公告)日：2008-04-24
申请号：US11974774
申请日：2007-10-16
申请人： Dong-Ho Ahn , Hideki Horii , Jong-Chan Shin , Jun-Soo Bae , Hyeong-Geun An
发明人： Dong-Ho Ahn , Hideki Horii , Jong-Chan Shin , Jun-Soo Bae , Hyeong-Geun An
IPC分类号： H01L45/00 , H01L21/06
CPC分类号： H01L45/143 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1226 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating layer. The phase change pattern contacts a top of the first plug electrode and a first potion of a top of the second plug electrode. An interconnection is electrically connected to a second portion of the top of the second plug electrode.
摘要翻译：提供了一种相变存储器件及其形成方法。根据相变存储器，第一插头电极和第二插头电极在模具绝缘层中彼此间隔开。相变图案设置在模具绝缘层上。相变图案接触第一插头电极的顶部和第二插头电极的顶部的第一部分。互连电连接到第二插头电极的顶部的第二部分。

37. 发明授权

US06740531B2 Method of fabricating integrated circuit devices having dielectric regions protected with multi-layer insulation structures 有权
标题翻译：制造具有由多层绝缘结构保护的电介质区域的集成电路器件的方法
公开(公告)号：US06740531B2
公开(公告)日：2004-05-25
申请号：US09923670
申请日：2001-03-07
申请人： Hag-ju Cho , Hyeong-geun An
发明人： Hag-ju Cho , Hyeong-geun An
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L28/55
摘要： A dielectric region, such as a ferroelectric dielectric region of an integrated circuit capacitor, is protected by a multi-layer insulation structure including a first relatively thin insulation layer, e.g., an aluminum oxide or other metal oxide layer, and a second, thicker insulating layer, e.g., a second aluminum oxide or other metal oxide layer. Before formation of the second insulation layer, the first insulation layer and the dielectric preferably annealed, which can increase a remnant polarization of the dielectric region. The first insulation layer can serve as a hydrogen diffusion barrier during formation of the second insulation layer and other overlying structures. In this manner, degradation of the dielectric can be reduced. Devices and fabrication methods are discussed.
摘要翻译：诸如集成电路电容器的铁电电介质区域的电介质区域由包括第一相对薄的绝缘层（例如，氧化铝或其它金属氧化物层）的多层绝缘结构和第二较厚绝缘层层，例如第二氧化铝或其它金属氧化物层。在形成第二绝缘层之前，第一绝缘层和电介质优选退火，这可以增加电介质区域的剩余极化。第一绝缘层可以在形成第二绝缘层和其它上覆结构期间用作氢扩散阻挡层。以这种方式，可以降低电介质的劣化。讨论了器件和制造方法。

38. 发明授权

US08644062B2 Multi-level memory device using resistance material 有权
标题翻译：使用电阻材料的多级存储器件
公开(公告)号：US08644062B2
公开(公告)日：2014-02-04
申请号：US12819498
申请日：2010-06-21
申请人： Ik-Soo Kim , Sung-Lae Cho , Do-Hyung Kim , Hyeong-Geun An , Dong-Hyun Im , Eun-Hee Cho
发明人： Ik-Soo Kim , Sung-Lae Cho , Do-Hyung Kim , Hyeong-Geun An , Dong-Hyun Im , Eun-Hee Cho
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C8/08 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0061 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/72 , H01L27/101 , H01L27/1021
摘要： A multi-level memory device includes an insulating layer having an opening therein, and a multi-level cell (MLC) formed in the opening that has a resistance level varies based on the data stored therein. The MLC is configured to have a resistance level that varies as write pulses having the same pulse height and different pulse widths are applied to the MLC.
摘要翻译：多级存储器件包括其中具有开口的绝缘层，并且形成在开口中的具有电阻电平的多电平单元（MLC）基于存储在其中的数据而变化。 MLC被配置为具有随着具有相同脉冲高度和不同脉冲宽度的写入脉冲被施加到MLC而变化的电阻电平。

39. 发明申请

US20130234100A1 NONVOLATILE MEMORY CELLS HAVING PHASE CHANGEABLE PATTERNS THEREIN FOR DATA STORAGE 审中-公开
标题翻译：具有数据存储的相位可变图案的非易失性存储器单元
公开(公告)号：US20130234100A1
公开(公告)日：2013-09-12
申请号：US13860836
申请日：2013-04-11
申请人： Hyeong-Geun An , Dong-Ho Ahn , Young-Soo Lim , Yong-Ho Ha , Jun-Young Jang , Dong-Won Lim , Gyeo-Re Lee , Joon-Sang Park , Han-Bong Ko , Young-Lim Park
发明人： Hyeong-Geun An , Dong-Ho Ahn , Young-Soo Lim , Yong-Ho Ha , Jun-Young Jang , Dong-Won Lim , Gyeo-Re Lee , Joon-Sang Park , Han-Bong Ko , Young-Lim Park
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/141 , H01L45/16 , Y10S438/90
摘要： Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction.
摘要翻译：相变存储器件可以在衬底上具有底部图案。线形或L形底部电极可以形成为与衬底上的相应底部图案接触并且具有由衬底上沿x和y轴方向的尺寸限定的顶表面。沿着底部电极的顶表面的x轴的尺寸比用于制造相变存储器件的光刻工艺的分辨率极限具有更小的宽度。相变图案可以形成为与底部电极的顶表面接触以具有比底部电极的顶表面的x和y轴方向上的每个尺寸更大的宽度，并且顶部电极可以形成在相位上其中线形或L形表示底部电极在x轴方向上的截面线形状或截面L形。

40. 发明授权

US08426840B2 Nonvolatile memory cells having phase changeable patterns therein for data storage 有权
标题翻译：其中具有用于数据存储的相变图案的非易失性存储单元
公开(公告)号：US08426840B2
公开(公告)日：2013-04-23
申请号：US12913099
申请日：2010-10-27
申请人： Hyeong-Geun An , Dong-Ho Ahn , Young-Soo Lim , Yong-Ho Ha , Jun-Young Jang , Dong-Won Lim , Gyeo-Re Lee , Joon-Sang Park , Han-Bong Ko , Young-Lim Park
发明人： Hyeong-Geun An , Dong-Ho Ahn , Young-Soo Lim , Yong-Ho Ha , Jun-Young Jang , Dong-Won Lim , Gyeo-Re Lee , Joon-Sang Park , Han-Bong Ko , Young-Lim Park
IPC分类号： H01L47/00
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/141 , H01L45/16 , Y10S438/90
摘要： A nonvolatile memory cell includes a substrate and a phase changeable pattern configured to retain a state of the memory cell, on the substrate. An electrically insulating layer is provided, which contains a first electrode therein in contact with the phase changeable pattern. The first electrode has at least one of an L-shape when viewed in cross section and an arcuate shape when viewed from a plan perspective. A lower portion of the first electrode may be ring-shaped when viewed from the plan perspective. The lower portion of the first electrode may also have a U-shaped cross-section. An upper portion of the first electrode may also have an arcuate shape that spans more than 180° of a circular arc.
摘要翻译：非易失性存储单元包括衬底和配置为将存储单元的状态保持在衬底上的相变图案。提供电绝缘层，其包含与相变图案接触的第一电极。第一电极在从横截面观察时具有L形中的至少一个，并且从平面图看为弧形。从平面图看，第一电极的下部可以是环状的。第一电极的下部也可以具有U形横截面。第一电极的上部也可以具有跨越180°以上圆弧的弓形形状。

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