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31. 发明授权

US08072811B2 NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array 失效
标题翻译：基于NAND的NMOS NOR闪存单元，基于NAND的NMOS NOR闪存阵列，以及形成基于NAND的NMOS NOR闪存阵列的方法
公开(公告)号：US08072811B2
公开(公告)日：2011-12-06
申请号：US12387771
申请日：2009-05-07
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/30 , G11C2211/5641 , H01L27/11519 , H01L27/11521 , H01L27/11524 , Y10T29/41
摘要： A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
摘要翻译： NOR闪存非易失性存储器件提供NAND闪存非易失性存储器件的存储单元尺寸和低电流程序处理以及NOR非易失性存储器件的快速，异步随机存取。 NOR闪存非易失性存储器件具有NOR非易失性存储器电路阵列，其包括串联连接在NAND串中的电荷保持晶体管，使得至少一个电荷保持晶体管用作选择栅极晶体管，以防止漏电流通过电荷保持当电荷保持晶体管未被选择用于读取时，晶体管。最上面的电荷保持晶体管的漏极连接到与电荷保持晶体管平行的位线，并且最下面的电荷保持晶体管的源极连接到源极线并且平行于位线。电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

32. 发明申请

US20090316487A1 Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array 失效
标题翻译：用于抑制阵列中非选择性非易失性存储器单元中的多余泄漏电流的装置和方法
公开(公告)号：US20090316487A1
公开(公告)日：2009-12-24
申请号：US12456744
申请日：2009-06-22
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/06 , G11C16/04 , G11C7/00
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0491 , G11C16/10 , G11C16/3436 , G11C2211/5621 , G11C2211/5641 , G11C2211/565
摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing sub-threshold leakage current through unselected nonvolatile memory cells. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing sub-threshold leakage current through unselected nonvolatile memory cells.
摘要翻译：用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时使通过未选择的非易失性存储单元的亚阈值泄漏电流最小化。该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元，以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时使通过未选择的非易失性存储单元的亚阈值泄漏电流最小化。

33. 发明授权

US07372736B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07372736B2
公开(公告)日：2008-05-13
申请号：US11391662
申请日：2006-03-28
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , H01L29/76 , H01L23/544
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

34. 发明授权

US07120064B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US07120064B2
公开(公告)日：2006-10-10
申请号：US11036961
申请日：2005-01-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

35. 发明授权

US07102929B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07102929B2
公开(公告)日：2006-09-05
申请号：US11036835
申请日：2005-01-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

36. 发明申请

US20060176738A1 Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 审中-公开
公开(公告)号：US20060176738A1
公开(公告)日：2006-08-10
申请号：US11391170
申请日：2006-03-28
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

37. 发明申请

US20060171203A1 Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：新颖的单片，组合非易失性存储器允许字节，页和块写入，在单元阵列中没有干扰和分割，使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US20060171203A1
公开(公告)日：2006-08-03
申请号：US11376076
申请日：2006-03-15
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

38. 发明授权

US07064978B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07064978B2
公开(公告)日：2006-06-20
申请号：US10351180
申请日：2003-01-24
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , H01L29/76 , H01L23/544
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

39. 发明授权

US06906376B1 EEPROM cell structure and array architecture 有权
标题翻译： EEPROM单元结构和阵列架构
公开(公告)号：US06906376B1
公开(公告)日：2005-06-14
申请号：US10170492
申请日：2002-06-13
申请人： Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/34 , G11C16/04 , H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0433
摘要： An EEPROM cell device on a substrate is achieved. The device comprises, first, a selection transistor having gate, drain, source, and channel. The drain is defined as a cell bit line. An isolation transistor has gate, drain, source, and channel. The source is defined as a cell source line. Finally, a floating gate transistor has control gate, floating gate, drain, source, and channel. The drains and sources of each transistor comprise a diffusion layer in the substrate. The channels of each transistor comprise the substrate. The floating gate transistor drain is coupled to the selection transistor source. The floating gate transistor source is coupled to the isolation transistor drain. The device is programmed and erased by charge tunneling between the floating gate and the floating gate transistor channel. The device may further comprise an isolation well underlying the diffusion layer. A two transistor EEPROM cell is disclosed. Several array architectures using the EEPROM cell are disclosed.
摘要翻译：实现了基板上的EEPROM单元装置。该器件首先包括具有栅极，漏极，源极和沟道的选择晶体管。漏极定义为单元位线。隔离晶体管具有栅极，漏极，源极和沟道。源被定义为单元格源行。最后，浮栅晶体管具有控制栅极，浮栅，漏极，源极和沟道。每个晶体管的漏极和源极在衬底中包括扩散层。每个晶体管的通道包括衬底。浮栅晶体管漏极耦合到选择晶体管源极。浮栅晶体管源耦合到隔离晶体管漏极。该器件通过浮置栅极和浮动栅晶体管沟道之间的电荷隧道进行编程和擦除。该装置还可以包括扩散层下面的隔离阱。公开了一种双晶体管EEPROM单元。公开了使用EEPROM单元的几种阵列架构。

40. 发明申请

US20050122776A1 Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：新颖的单片，组合非易失性存储器允许字节，页和块写入，在单元阵列中没有干扰和分割，使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US20050122776A1
公开(公告)日：2005-06-09
申请号：US11036945
申请日：2005-01-14
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C11/34 , G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

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