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31. 发明授权

US07063744B2 Coating device 失效
标题翻译：涂装装置
公开(公告)号：US07063744B2
公开(公告)日：2006-06-20
申请号：US11206343
申请日：2005-08-18
申请人： Hiroshi Komatsu , Gen Okano
发明人： Hiroshi Komatsu , Gen Okano
IPC分类号： B05C1/14 , B32B37/12
CPC分类号： B05C1/14 , B05C1/022 , Y10S118/03
摘要： There is provided a coating device which can quickly cope with a change in size of a container. A pair of coating belts (annular belts) (11, 15) are arranged on two sides of a conveyor (10). The coating belt (15) is rotated at a high speed while the coating belt (11) is rotated at a low speed. A container (bottle) (1) on the conveyor (10) is coated while being rotated. When the size of the container (1) is to be changed, a pressing roller (57) is moved by an adjusting mechanism (50) in accordance with the size of the container (1).
摘要翻译：提供了能够快速应对容器尺寸变化的涂布装置。一对涂布带（环形带）（11,15）布置在输送机（10）的两侧。当涂布带（11）以低速旋转时，涂布带（15）以高速旋转。输送机（10）上的容器（瓶）（1）被旋转涂覆。当要改变容器（1）的尺寸时，根据容器（1）的尺寸，通过调节机构（50）使加压辊（57）移动。

32. 发明授权

US06773970B2 Method of producing a semiconductor device having improved gate structure 失效
标题翻译：制造具有改善的栅极结构的半导体器件的方法
公开(公告)号：US06773970B2
公开(公告)日：2004-08-10
申请号：US10368994
申请日：2003-02-19
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L21/2652 , H01L21/3141 , H01L21/3185 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/78621
摘要： A method of producing a semiconductor device able to prevent outward diffusion of an impurity from a gate electrode and improve the device quality, the method comprising the steps of forming a gate electrode made of a semiconductor layer on a substrate (preferably SOI substrate) via a gate insulating film, forming a first insulating film coating the gate electrode by ALD, forming a second insulating film on a first insulating film, introducing an impurity to a substrate (preferably silicon active layer of the SOI wafer) to form a source/drain region by self-alignment with respect to the gate electrode, and forming an interlayer insulating film on the second insulating film.
摘要翻译：一种制造能够防止杂质从栅电极向外扩散并提高器件质量的半导体器件的方法，该方法包括以下步骤：在衬底（优选SOI衬底）上形成由半导体层制成的栅电极形成通过ALD涂覆栅电极的第一绝缘膜，在第一绝缘膜上形成第二绝缘膜，将杂质引入衬底（优选SOI晶片的硅有源层）以形成源极/漏极区域通过对栅电极进行自对准，并在第二绝缘膜上形成层间绝缘膜。

33. 外观设计

USD487476S1 Camera 失效
公开(公告)号：USD487476S1
公开(公告)日：2004-03-09
申请号：US29163711
申请日：2002-07-11
申请人： Hiroshi Komatsu
设计人： Hiroshi Komatsu

34. 外观设计

USD482714S1 Camera 失效
公开(公告)号：USD482714S1
公开(公告)日：2003-11-25
申请号：US29163710
申请日：2002-07-11
申请人： Hiroshi Komatsu
设计人： Hiroshi Komatsu

35. 发明授权

US06541345B1 Semiconductor device with SOI structure 失效
公开(公告)号：US06541345B1
公开(公告)日：2003-04-01
申请号：US09071837
申请日：1998-05-04
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： H01L21331
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/78636 , H01L29/78648
摘要： Disclosed is a semiconductor device including a SOI substrate having a SOI layer, in which a structure made from a semiconductor device is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidation preventive film formed both on the SOI layer and on a region in which a contact reaching the structure is to be formed; an interlayer dielectric film formed on the structure, the SOI layer and the thick oxide film; and a plurality of connection holes formed in the interlayer dielectric film and including at least a connection hole positioned on the region in which the contact is to be formed. With this semiconductor device, a contact reaching a back gate electrode can be formed without increasing an aspect ratio of the contact even when a thick oxide film is grown on the back gate electrode in the filed area by selectively oxidizing the back gate electrode in the field area.

36. 发明授权

US06342717B1 Semiconductor device and method for producing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06342717B1
公开(公告)日：2002-01-29
申请号：US09499610
申请日：2000-02-07
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： H01L2972
CPC分类号： H01L29/78648 , H01L21/823437 , H01L21/823462 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/4908
摘要： A semiconductor device improving the characteristics of an integrated circuit in which transistors of different operation modes including a dynamic Vth MOS (DV-MOS) are mixed, comprising a plurality of MOSFETs each including a semiconductor active layer formed in an insulating layer on a substrate, a back side gate electrode facing its substrate side surface via a back side gate insulating film, and a front side gate electrode facing the opposite side surface from the semiconductor active layer via a front side gate insulating film, the plurality of MOSFETs including a first MOSFET (CON-MOS) in which the back side gate electrode and the front side gate electrode are insulated and separated from each other and a second MOSFET (DV-MOS) in which the back side gate electrode and the front side gate electrode are electrically connected, the back side gate insulating film of the DV-MOS being thinner than the back side gate insulating film of the CON-MOS.
摘要翻译：一种改进其中混合包括动态Vth MOS（DV-MOS）的不同工作模式的晶体管的集成电路的特性的半导体器件，包括多个MOSFET，每个MOSFET包括形成在衬底上的绝缘层中的半导体有源层，经由背面栅极绝缘膜与其基板侧表面相对的背面侧栅电极以及经由前侧栅极绝缘膜与所述半导体有源层相对的相对侧面的前侧栅电极，所述多个MOSFET包括第一MOSFET （CON-MOS），其中背面栅极电极和前侧栅电极彼此绝缘和分离;以及第二MOSFET（DV-MOS），其中背侧栅极电极和前侧栅电极电连接，DV-MOS的背面侧栅极绝缘膜比CON-MOS的背面栅极绝缘膜薄。

37. 发明授权

US06259502B1 In-plane switching mode liquid crystal display device having a common electrode on the passivation layer 失效
标题翻译：在钝化层上具有公共电极的面内切换模式液晶显示装置
公开(公告)号：US06259502B1
公开(公告)日：2001-07-10
申请号：US09114302
申请日：1998-07-10
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： G02F11343
CPC分类号： G02F1/134363 , G02F1/136213
摘要： An in-plane switching mode liquid crystal display device comprises a substrate, a pixel region, a common bus line, a thin film transistor, a data electrode, a passivation layer over the data electrode and the thin film transistor, and a common electrode. The pixel region lies on the substrate. The common bus line is aligned in the pixel region. The thin film transistor is coupled to the pixel region and the pixel regions comprises a gate electrode and a gate insulator having a portion overlying the gate electrode. The data electrode lies over the gate insulator and has a portion overlying the common bus line to form a first storage capacitor. The passivation layer overlies the data electrode and the thin film transistor. The common electrode overlies the passivation layer and has a portion overlying the data electrode to form a second storage capacitor.
摘要翻译：面内切换模式液晶显示装置包括基板，像素区域，公共总线，薄膜晶体管，数据电极，数据电极和薄膜晶体管上的钝化层以及公共电极。像素区域位于基板上。公共总线在像素区域中对齐。薄膜晶体管耦合到像素区域，并且像素区域包括栅极电极和栅极绝缘体，栅极绝缘体具有覆盖栅电极的部分。数据电极位于栅极绝缘体上方，并且具有覆盖公共总线的部分以形成第一存储电容器。钝化层覆盖数据电极和薄膜晶体管。公共电极覆盖钝化层并且具有覆盖数据电极的部分以形成第二存储电容器。

38. 发明授权

US5981376A Method of forming viahole 失效
标题翻译：通孔形成方法
公开(公告)号：US5981376A
公开(公告)日：1999-11-09
申请号：US733192
申请日：1996-10-17
申请人： Hiroshi Komatsu , Makoto Hashimoto , Motoaki Nakamura
发明人： Hiroshi Komatsu , Makoto Hashimoto , Motoaki Nakamura
IPC分类号： H01L21/28 , H01L21/768 , H01L23/522 , H01L21/3213
CPC分类号： H01L21/76814 , H01L21/76802 , H01L21/76831
摘要： A method of forming a viahole in an interlayer insulating film without the formation of irregularities on a side wall of the viahole. The method includes a first step of forming a viahole in an interlayer insulating film having a multi-layer structure of plural kinds of insulating layers; a second step of forming a side wall film on a side wall of the viahole; and a third step of removing a native oxide film formed on a bottom portion of the viahole by etching.
摘要翻译：在层间绝缘膜中形成通孔的方法，而不会在通孔的侧壁上形成凹凸。该方法包括在具有多种绝缘层的多层结构的层间绝缘膜中形成通孔的第一步骤; 在通孔的侧壁上形成侧壁膜的第二步骤; 以及通过蚀刻除去形成在通孔的底部上的自然氧化膜的第三步骤。

39. 发明授权

US5619057A Complex film overlying a substrate with defined work function 失效
标题翻译：复合膜覆盖具有规定功函数的基板
公开(公告)号：US5619057A
公开(公告)日：1997-04-08
申请号：US634951
申请日：1996-04-19
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L23/485 , H01L23/532 , H01L29/45 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28518 , H01L21/28525 , H01L21/76843 , H01L21/76855 , H01L21/76859 , H01L21/76864 , H01L23/485 , H01L23/53223 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/4975 , H01L29/6659 , H01L2924/0002
摘要： Disclosed is a method and an apparatus for making devices with low barrier height. In fabricating an n-channel and p-channel devices, hemisphere grains, silicon crystal grains and metal silicide crystal grains are formed on a contact-hole or a gate electrode on an insulating film in each semiconductor element, so that it becomes possible to control the work function, to reduce the contact resistance, and to control the threshold voltage V.sub.th.
摘要翻译：公开了一种用于制造屏障高度低的装置的方法和装置。在制造n沟道和p沟道器件时，在每个半导体元件中的绝缘膜上的接触孔或栅电极上形成半球晶粒，硅晶粒和金属硅化物晶粒，使得可以控制工作功能，降低接触电阻，并控制阈值电压Vth。

40. 发明授权

US5332627A Field emission type emitter and a method of manufacturing thereof 失效
标题翻译：场致发射型发射体及其制造方法
公开(公告)号：US5332627A
公开(公告)日：1994-07-26
申请号：US783165
申请日：1991-10-28
申请人： Hidetoshi Watanabe , Hiroshi Komatsu , Toshiaki Hasegawa , Toshiyuki Ishimaru
发明人： Hidetoshi Watanabe , Hiroshi Komatsu , Toshiaki Hasegawa , Toshiyuki Ishimaru
IPC分类号： H01J1/304 , H01J9/02 , B32B9/00
CPC分类号： H01J9/025 , H01J1/3042 , Y10S428/901 , Y10T428/12174 , Y10T428/24273
摘要： A field emission type emitter comprises: a conductive substrate; an insulating film formed on the conductive substrate; a cavity formed in the insulating film; a cathode formed on the conductive substrate in the cavity; and a gate electrode formed over the insulating film. The gate electrode is preferably made of refractory metal silicide. A polycrystalline silicon film is preferably formed between the gate electrode and the insulating film. The side walls of the insulating film in the portion of the cavity preferably have an inverse tapered shape.In the case where a glass substrate is used, a conductive film is formed on the glass substrate through an insulating film and the cathode is formed on the conductive film in the cavity. Manufacturing methods of the field emission type emitter are also disclosed.
摘要翻译：场发射型发射器包括：导电衬底; 形成在导电性基板上的绝缘膜; 形成在绝缘膜中的空腔; 形成在空腔中的导电基板上的阴极; 以及形成在绝缘膜上的栅电极。栅电极优选由难熔金属硅化物制成。优选在栅电极和绝缘膜之间形成多晶硅膜。绝缘膜在空腔部分中的侧壁优选具有倒锥形形状。在使用玻璃基板的情况下，通过绝缘膜在玻璃基板上形成导电膜，阴极形成在空腔的导电膜上。还公开了场致发射型发射体的制造方法。

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